Analog IC Parasitic Constraint Verification
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Solution Overview
Problem
The existing design processes for analog integrated circuits (ICs) face challenges in ensuring parasitic constraints are met during the design process, leading to lengthy simulations and potential non-convergence due to the large number of parasitic components required for full parasitic extraction, which can occur after the layout is completed, and lack of mechanisms to specify global constraints.
Innovation Solution
A method and apparatus that involve creating a schematic with attached parasitic constraints, extracting parasitic values from the layout, and comparing them to verify compliance, using a parasitic constraint analyzer with a constraint manager to associate constraints and a constraint confirmer to check compliance, allowing for simulation with expected parasitic values rather than large numbers of extracted components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full parasitic extraction is performed to ensure compliance with parasitic constraints, then measurement precision of parasitic values is improved, but simulation time increases and simulations may not converge
Solution Approach 1:
The patent extracts only the necessary parasitic values from layout data and attaches them directly to the schematic diagram, rather than performing full parasitic extraction with all possible parasitic components. This selective extraction approach maintains measurement precision for critical parasitic values while significantly reducing simulation time and avoiding convergence issues.
Solution Approach 2:
The patent applies partial action by performing parasitic extraction only for specific nets or components where parasitic constraints are defined, rather than extracting all parasitic values from the entire layout. This allows the design process to obtain sufficient parasitic information for verification without the overhead of complete extraction.
2Reliability
If full parasitic extraction is performed to verify specifications, then reliability of design verification is improved, but device complexity increases due to adding thousands of parasitic components
Solution Approach 1:
The patent extracts parasitic values from layout data and attaches them directly to the schematic diagram as annotations rather than adding physical parasitic components to the circuit. This maintains verification reliability by preserving the parasitic information needed for accurate simulation while avoiding the complexity of managing thousands of additional circuit components.
Solution Approach 2:
The patent creates a copy of the parasitic information from the layout data and attaches it to the schematic diagram. This copying approach allows the parasitic values to be used for verification purposes without modifying the original circuit design or adding complex parasitic components to the schematic.
3Measurement precision
If parasitic values are extracted after layout completion to verify compliance, then measurement precision is improved, but loss of time increases because problems are detected late in the design process
Solution Approach 1:
The patent performs parasitic extraction and attaches parasitic values to the schematic diagram during the layout design phase, before final verification is needed. This preliminary action allows parasitic constraints to be checked earlier in the design process, enabling designers to identify and correct issues before committing to the final layout, thereby reducing overall design cycle time while maintaining measurement precision.
4Ease of manufacture
If selected nets extraction is used to reduce extraction difficulties, then ease of manufacture is improved, but measurement precision deteriorates because not all parasitic values are captured
Solution Approach 1:
The patent applies local quality by performing parasitic extraction selectively for specific nets or components where parasitic constraints are defined, rather than uniformly extracting all parasitic values. This allows the extraction process to focus computational resources on critical areas, maintaining measurement precision where needed while improving ease of manufacture by avoiding unnecessary extraction of non-critical parasitic values.
Data Source
AI summary
A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on a set of specifications, (2) attaching parasitic constraints to the schematic, (3) creating a layout of the analog integrated circuit based on the schematic including the parasitic constraints, (4) extracting parasitic values from parasitic elements of the layout and (5) comparing the extracted parasitic values with the parasitic constraints to verify compliance therewith.