Analog Neural Inference Crossbar That Overcomes Line Resistance Limits
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Solution Overview
Problem
Conventional analog approximation devices for neural networks are limited by the low ratio of resistance of memory cells to resistance of connection lines, restricting the size of network layers and severely limiting prediction power.
Innovation Solution
Implementing a crossbar-based analog acceleration with balanced tree connection lines, high-resistance memory cells, and specific properties like SOT MTJ technology, quantum materials, and controlled parasitic currents to overcome resistance limitations, allowing larger neural network layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional crossbar-based analog approximation is used, then energy efficiency is improved, but the size of network layers is limited by the low ratio of resistance of memory cells to resistance of connection lines
Solution Approach 1:
The patent introduces compensation circuits at specific locations (local) in the crossbar array to counteract the effects of parasitic resistances. These circuits are strategically placed to compensate for voltage drops and current distribution errors in specific regions, thereby extending the usable network layer size without sacrificing energy efficiency.
Solution Approach 2:
The patent implements feedback mechanisms where the output currents are measured and used to adjust subsequent operations. This feedback allows the system to correct for errors introduced by parasitic resistances, enabling larger network layers to be processed accurately while maintaining the energy efficiency benefits of analog computation.
2Measurement precision
If the size of network layers is increased to improve prediction power, then prediction accuracy is improved, but the low resistance ratio limits the maximum achievable layer size
Solution Approach 1:
The patent introduces intermediary compensation circuits that act as mediators between the memory cells and the readout circuits. These intermediaries correct the distorted current signals caused by parasitic resistances, thereby maintaining prediction accuracy for larger network layers while preserving the reliability of the analog approximation.
Solution Approach 2:
The patent dynamically adjusts operational parameters such as voltage levels and current thresholds based on the detected parasitic effects. By changing these parameters adaptively, the system maintains reliable approximation even as network layer size increases beyond conventional limits.
3Adaptability or versatility
If larger network layers are implemented, then prediction power is improved, but parasitic currents and resistance effects become more severe
Solution Approach 1:
The patent converts the harmful parasitic currents into useful information by measuring their effects and using this information to compensate for errors. The parasitic resistance effects, which normally degrade performance, are measured and used to calibrate and correct subsequent operations, thereby enabling larger network layers to function accurately.
Solution Approach 2:
The patent implements feedback loops that continuously monitor and correct for parasitic current effects. By measuring the actual current distribution and comparing it to expected values, the system can identify and compensate for errors caused by parasitic resistances, maintaining prediction power in larger networks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable instant analog approximation of neural network layers up to 30 times larger than conventional designs, with improved energy efficiency and prediction accuracy.
Implementation Method 1
writing is performed by means of spin-orbit torque, not by means of direct current through the cell
Implementation Method 2
Magnetic Tunnel Junction (MTJ) based non-volatile memory
Implementation Method 3
A grid of resistive memory cells produces output currents, representing the results of MAC operations in accordance to Ohm's and Kirchhoff's laws for the multiplication of cell's conductivity, representing neural network weights, by voltage levels, representing the neural network's layer inputs
Implementation Method 4
A grid of resistive memory cells produces output currents, representing the results of MAC operations in accordance to Ohm's and Kirchhoff's laws for the multiplication of cell's conductivity, representing neural network weights, by voltage levels, representing the neural network's layer inputs
Data Source
AI summary
Apparatus including a plurality of non-volatile memory cells of variable resistance organized to perform an instant analog approximation for a reliable neural network inference. by a current distribution governed by conductivity of the circuit elements. of an output for a neural network layer of a size not limited, within the common neural network inference practice, by the ratio of resistance of memory cells to the resistance of connection lines. The apparatus includes a plurality of connection lines and may further include a plurality of control celis/devices to organize an ensemble of non-volatile memory cells of variable resistance to perform the reliable instant analog approximation of the output for the neural network layer of the size not practically limited by the ratio of resistance of memory cells to the resistance of connection lines.