Analog Interleaver Gain Paths for Clock Feedthrough Cancellation
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Solution Overview
Problem
Existing digital-to-analog converters face challenges in achieving high-speed conversion rates above 50 Gs/s due to bandwidth limitations and distortion issues when interleaving signals, resulting in limited bandwidth generation and clock feedthrough.
Innovation Solution
A method and device for interleaving digital signals using a dual-path architecture with variable gain stages and clock phase shifting, which cancels clock feedthrough and allows for simultaneous interleaving and equalization, enabling higher bandwidth generation without altering the signal spectrum.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If addition interleaving of two 180 degree spaced DACs is used, then the sampling images are canceled and the spectrum appears to be generated by a single DAC running at 2*fs, but the sinc function is still zero at fs causing distortion and limiting bandwidth to below fs/2
Solution Approach 1:
The patent changes the parameters of the interleaving process by introducing different gain factors (a and b) for different signal paths and using phase-shifted clock signals. This modifies the combination process to avoid the zero-crossing issue at fs while maintaining the cancellation of sampling images, thereby enabling full bandwidth utilization up to 2*fs.
Solution Approach 2:
The patent combines multiple signal paths with different characteristics (different gains, different phase shifts) into a composite interleaved output. This composite approach allows the system to achieve the benefits of both image cancellation and full bandwidth operation by carefully designing the combination of multiple processed signals.
2Productivity
If switching multiplexer interleaver is used, then one signal is chosen for one part of the clock cycle and the other input for the other part, but clock feedthrough occurs resulting in extra mixing products between the wanted signal and the DAC clock frequency
Solution Approach 1:
The patent introduces gain stages and phase-shifted clock signals as intermediaries between the input signals and the final combined output. These intermediaries process the signals in a way that avoids direct switching-induced feedthrough, thereby eliminating the harmful mixing products while maintaining high-speed interleaving capability.
Solution Approach 2:
The patent replaces the mechanical switching action of the multiplexer with an analog signal processing approach using gain stages and phase-shifted clock signals. This substitution eliminates the abrupt switching transitions that cause clock feedthrough, replacing them with continuous analog processing that avoids generating harmful mixing products.
3Speed
If two lower speed DACs are combined to achieve higher speed, then the sample rate is increased, but the required bandwidth of the DAC and channel becomes a limiting factor
Solution Approach 1:
The patent segments the high-speed conversion task into multiple lower-speed DACs operating in parallel with interleaved timing. Each DAC operates at a manageable speed, and their outputs are combined through the gain-stage and phase-shifted clock signal processing to achieve the overall high conversion rate without requiring any single DAC to operate at the full high speed, thereby managing bandwidth requirements effectively.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively interleaves and equalizes signals, achieving a full-rate output equivalent to a single high-speed DAC, with no additional frequency spurs or spectrum alteration, and includes a built-in feed-forward equalizer to compensate for bandwidth limitations.
Implementation Method 1
a mixer and a second gain stage adapted for multiplying a signal coming from the input terminal with a predefined or modifiable second gain (b) before or after mixing it with a clock signal using the mixer to obtain a second signal
Data Source
AI summary
An interleaver for combining at least two incoming signals into an analog output signal includes at least a first signal path and a second signal path. Each signal path has: an input terminal, a first gain stage for multiplying a signal coming from the input terminal with a first gain (a) to obtain a first signal, a mixer and a second gain stage for multiplying a signal coming from the input terminal with a second gain (b) before or after mixing it with a clock signal to obtain a second signal, an adder for adding the first and second signal to obtain an output signal of the signal path wherein the first and second gain are different from zero. The interleaver comprises an adder for adding the output signals from the signal paths.