Analog In-Memory MAC Unit Using C-2C Ladder Multibit Computing

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Solution Overview

Problem

Conventional computation architectures face challenges in integrating MAC operation units with memory units due to a significant imbalance in transistor count, leading to high latency and energy consumption, particularly in non-Von Neumann architectures where memory and processing units are separated, resulting in inefficient data transfer and energy overhead.

Innovation Solution

An in-memory computing architecture that integrates a MAC unit with memory cells using analog computing methods, employing a C-2C ladder-based analog MAC unit for multibit operations, reducing the transistor count imbalance and minimizing data fetches by merging the MAC unit with the memory array.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If digital MAC operation units are integrated with memory units, then computing capability is improved, but the transistor count imbalance makes integration difficult

Engineering Contradiction:

Improvecomputing capabilityVSAvoidtransistor count imbalance

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the MAC operation unit with the memory unit into a single integrated structure. The MAC unit shares physical space and resources with the memory array, allowing simultaneous storage and computation functions. This merging resolves the transistor count imbalance by co-locating the computing elements with memory elements rather than treating them as separate entities.

Inventive Principle:

Principle #5Merging (Combining)

2Device complexity

If memory and processing units are separated in von-Neumann architectures, then device structure is simplified, but data transfer latency and energy consumption increase

Engineering Contradiction:

Improvedevice structureVSAvoiddata transfer latency

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent combines memory storage functions with MAC computation functions into a single integrated unit. This eliminates the need for data to be physically transferred between separate memory and processing units, as the computation occurs directly within the memory structure. The merging resolves the latency issue by removing the data transfer step entirely.

Inventive Principle:

Principle #5Merging (Combining)

3Ease of operation

If data is serially fetched from storage layer by layer, then data access is simplified, but energy overhead and latency increase

Engineering Contradiction:

Improvedata accessVSAvoidenergy overhead

Core Design Contradiction:

Ease of operationVSUse of energy by stationary object

Solution Approach 1:

The patent replaces the mechanical/physical data fetching process with an in-situ computation approach. Instead of serially fetching data through physical movement between layers, the system performs MAC operations directly within the memory array using the stored data. This substitution eliminates the energy-intensive data transfer process while maintaining ease of access through direct computational operations.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12602200B2Analog multiply-accumulate unit for multibit in-memory cell computing

Publication Date: 2026.04.14 INTEL CORP

AI summary

Systems, apparatuses and methods include technology that receives, with a first plurality of multipliers of a multiply-accumulator (MAC), first digital signals from a memory array, wherein the first plurality of multipliers includes a plurality of capacitors. The technology further executes, with the first plurality of multipliers, multibit computation operations with the plurality of capacitors based on the first digital signals, and generates, with the first plurality of multipliers, a first analog signal based on the multibit computation operations.