Analog MAC Circuit With Capacitor Arrays for Low-Power AI Computing
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Solution Overview
Problem
Current processors face challenges in performing low-energy, low-delay multiply accumulate (MAC) operations for AI applications, leading to high power consumption, large area occupation, and accuracy issues due to digital signal processing.
Innovation Solution
A multi-bit analog multiplication and accumulation circuit system that performs multiplications and accumulations on four-bit input and weight data within one Computing in Memory (CIM) period using analog multiplication circuits with capacitor switch arrays and a binary place value combiner, reducing power consumption and area while improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital signal processing is used in current processors, then computational accuracy is maintained, but power consumption increases and computing delay increases
Solution Approach 1:
The patent replaces digital signal processing (electronic/computational system) with analog multiplication and accumulation circuits (electrical circuit system). The analog circuits perform MAC operations directly in the analog domain using capacitor switch arrays and accumulation lines, eliminating the need for digital conversion and processing steps, thereby reducing power consumption while maintaining computational accuracy.
Solution Approach 2:
The patent changes the operational parameter domain from digital to analog. By performing MAC operations in the analog domain with continuous voltage signals rather than discrete digital values, the system reduces power consumption and computing delay while maintaining accuracy through the analog nature of the computation.
2Measurement precision
If digital signal processing is used in current processors, then computational accuracy is maintained, but computing delay increases
Solution Approach 1:
The patent replaces digital signal processing with direct analog computation circuits. The analog multiplication circuits and accumulation lines perform MAC operations in continuous time, eliminating the sequential digital processing steps and conversion overhead, thereby reducing computing delay while preserving accuracy through analog computation.
Solution Approach 2:
The patent implements continuous analog computation rather than discrete digital processing. The analog circuits maintain continuous voltage signals throughout the MAC operation, allowing parallel processing without the sequential conversion and processing steps inherent in digital systems, thus reducing computing delay while maintaining accuracy.
3Measurement precision
If more components are added to perform MAC operations, then computational accuracy is improved, but circuit area increases
Solution Approach 1:
The patent merges multiple functions into unified analog circuits. The capacitor switch arrays perform both multiplication and accumulation functions simultaneously, and the accumulation lines aggregate results from multiple parallel circuits. This integration achieves high computational accuracy through multi-bit parallel processing while minimizing circuit area by eliminating redundant digital conversion and processing components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system achieves low power consumption, reduced computational delays, and enhanced accuracy by performing MAC operations in analog form, avoiding errors from digital conversions and allowing for high-speed parallel computing.
Implementation Method 1
each analog multiplication circuit includes four capacitor switch arrays, each performing multiplications on one bit of the four-bit input data and the four-bit weight data
Implementation Method 2
a first accumulation line, a second accumulation line, a third accumulation line and a fourth accumulation line, wherein each accumulation line outputs an accumulation of multiplications performed by each capacitor switch array
Data Source
AI summary
A multi-bit analog multiplication and accumulation circuit system, which includes: a plurality of analog multiplication circuits, first to fourth accumulation lines, and a binary place value combiner. Each of the analog multiplication circuits performs multiplications on four-bit input data and four-bit weight data, wherein each of the analog multiplication circuits includes four capacitor and switch arrays for performing multiplications on one bit of the four-bit input data and the four-bit weight data. Each of the accumulation lines outputs an accumulation of multiplications performed by each capacitor switch array of each analog multiplication circuit on one bit of the four-bit input data and the four-bit weight data. The binary place value combiner sums up the accumulated result outputted from the accumulation line with corresponding binary place value.