Analog MAC Circuit Charge Sharing for Deep Learning Efficiency
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Solution Overview
Problem
Deep learning algorithms require efficient processing of numerous operations, but existing CPU and GPU configurations consume excessive power, and digital circuit-based solutions like FPGA waste area and increase power consumption.
Innovation Solution
A MAC operating device and method using a plurality of operation circuits with operation capacitors and switches, performing charge sharing between operation and division capacitors to update weight values for variables, optimizing operations through multiple phases for efficient processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU or GPU is used to process deep learning algorithm, then processing capability is improved, but electric power consumption increases hugely
Solution Approach 1:
The patent replaces the conventional digital circuit-based processing system (CPU/GPU) with an analog computing system that uses capacitors and switches to perform MAC operations. This substitution of the fundamental processing mechanism dramatically reduces power consumption while maintaining deep learning processing capability, directly resolving the contradiction between processing capability and power consumption.
Solution Approach 2:
The patent changes the operational parameters from digital voltage levels to analog charge quantities on capacitors. By representing data and weight values as charges on capacitors rather than digital signals, the system achieves efficient MAC operations with significantly lower power consumption, resolving the energy efficiency issue while preserving processing capability.
2Productivity
If FPGA or ASIC is used to process deep learning algorithm on mobile and IoT devices, then electric power consumption limit is overcome, but hardware area increases and power consumption increases
Solution Approach 1:
The patent segments the deep learning processing into multiple operation phases corresponding to different bit positions (LSB to MSB). Each phase processes one bit of the weight value, allowing the same hardware structure to be reused iteratively. This temporal segmentation reduces the need for parallel hardware resources, thereby reducing hardware area while maintaining processing efficiency.
Solution Approach 2:
The patent designs a universal operation circuit that can process multiple bits of weight values through different operation phases. The same capacitors and switches are reused across multiple phases to handle different bit positions, making the hardware multi-functional. This universality reduces hardware area compared to dedicated circuits for each bit position.
3Productivity
If digital circuit operation model is used with many transistors for complex multiplication, then processing is achieved, but area is wasted and power consumption increases
Solution Approach 1:
The patent replaces the transistor-based digital multiplication circuit with an analog charge-based multiplication mechanism. Instead of using many transistors to perform complex multiplication, the system uses capacitors to store charges representing input values and weight values, and switches to control charge transfer. This substitution dramatically reduces the hardware area required for multiplication operations while maintaining full multiplication capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces hardware integration complexity and power consumption while accurately processing deep learning operations, enhancing efficiency and area utilization.
Implementation Method 1
the plurality of operation circuits perform a plurality of operation phases for the updating through a charge sharing of the operation capacitor and the division capacitor by switching the plurality of switches at a determined time
Data Source
AI summary
A MAC operating device comprising a plurality of operation circuits respectively including an operation capacitor and a plurality of switches; and a division capacitor, wherein one end of the operation capacitor is respectively connected to a first operation switch connected to an input terminal and a first reset switch connected to a ground terminal, and the other end of the operation capacitor is connected to both a second operation switch connected to a division capacitor and a second reset switch connected to the ground terminal is provided.