Analog MAC Circuit Using Current Superposition for AI Computing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing AI accelerator architectures face challenges with high power consumption and large circuit area due to the use of digital domain logic gates for complex computations, limiting their ability to handle large volumes of data efficiently.
Innovation Solution
Implementing MAC circuitry that operates in the analog domain using current scaling and superposition, reducing power consumption and circuit size by utilizing current mirror circuits and computation nodes for efficient computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital domain logic gates are used for complex computations, then computational accuracy is improved, but power consumption and circuit area increase significantly
Solution Approach 1:
The patent replaces digital logic gate systems with analog circuit systems. Specifically, it uses operational amplifiers, resistors, capacitors, and other analog components to perform computational functions that would traditionally require digital logic gates, thereby reducing power consumption while maintaining computational capability
Solution Approach 2:
The patent changes the operating domain from digital to analog by modifying key parameters such as using continuous voltage levels instead of discrete logic levels, and employing analog signal processing techniques. This allows computations to be performed with lower power consumption while achieving satisfactory accuracy for AI applications
2Productivity
If digital domain logic gates are used for complex computations, then computational capability is improved, but circuit area increases significantly
Solution Approach 1:
The patent substitutes digital logic gate implementations with analog circuit implementations. By using operational amplifiers and passive components arranged in computational circuits, the system achieves high computational capability with significantly reduced circuit area compared to digital logic gate equivalents
Solution Approach 2:
The patent merges multiple computational functions into single analog circuits. For example, operational amplifiers perform multiple operations (amplification, addition, integration) simultaneously, and resistor networks perform both weighting and summing functions, thereby reducing the overall circuit area required for AI computations
3Use of energy by moving object
If analog domain computation is used, then power consumption and circuit area are reduced, but noise susceptibility increases
Solution Approach 1:
The patent incorporates noise mitigation measures directly into the analog circuit design. This includes using differential signaling to reject common-mode noise, implementing proper grounding schemes, and designing with appropriate signal conditioning stages that prevent noise accumulation before it becomes problematic
Solution Approach 2:
The patent introduces intermediary analog-to-digital conversion stages at strategic points in the computation pipeline. These ADCs convert analog signals to digital form to break up noise propagation paths, allowing subsequent digital processing to be more resistant to noise while maintaining the power and area benefits of analog computation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces power consumption and circuit area, enhancing computing capacity and accuracy for AI applications, allowing for more efficient and accurate data processing.
Implementation Method 1
the bias circuit includes a current mirror circuit. In some implementations, for each computation node, the current mirror circuit includes: an input transistor configured to receive analog input signal; a p-type metal–oxide–semiconductor (PMOS) output transistor configured to generate the positive bias current; and an n-type metal–oxide–semiconductor (NMOS) output transistor configured to generate the negative bias current
Implementation Method 2
the computation result current of that computation node is a superposition of i) a current at the output node of that computation node, and ii) a computation result current generated by an adjacent computation node in the computation matrix
Data Source
AI summary
An electronic circuit is provided. The electronic circuit includes a plurality of digital-to-analog converters (DACs) configured to generate a plurality of analog input signals. The electronic circuit includes a computation matrix coupled to the plurality of DACs and configured to receive the plurality of analog input signals from the plurality of DACs. The computation matrix comprises a plurality of computation nodes. Each computation node comprises: a bias circuit configured to generate a positive bias current and a negative bias current based on an analog input signal among the plurality of analog input signals, and a computation circuit configured to generate a computation result current based on the positive bias current, the negative bias current, and a digital weight signal. An electronic device and a method are also provided.