Analog In-Memory MAC Arrays With PWM Gating for Low-Noise Sensing
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Solution Overview
Problem
Existing analog MAC implementations using flash memory cells suffer from errors due to charge coupling and opamp settling delays, which affect the accuracy of charge accumulation and sensing in neural networks.
Innovation Solution
Implementing Pulse Width Modulation (PWM) generators to control the Select Gate (SG) and Control Gate (CG) lines of flash cells, reducing errors by ensuring controlled transitions and minimizing parasitic coupling, and using a reference voltage to stabilize bit-line potentials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full rail-to-rail transition is applied on SG to enable flash cell, then flash cell activation is achieved, but charge coupling errors are introduced
Solution Approach 1:
The patent applies periodic action by using controlled pulse transitions on the SG line instead of continuous rail-to-rail transitions. The SG line is activated only during specific time windows when charge accumulation is required, and remains inactive otherwise, thereby reducing parasitic coupling while maintaining necessary flash cell activation
Solution Approach 2:
The patent implements preliminary action by pre-charging the SG line to VDD before the actual charge accumulation phase begins. This preliminary charging ensures that when the flash cell needs to be activated, the SG line is already at the required voltage level, enabling rapid and controlled activation without introducing additional transitions that would cause charge coupling errors
2Stability of the object's composition
If opamp transitions to settle bit-line voltage to bl_ref, then constant bit-line voltage is maintained, but settling delay occurs
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit-line to the reference voltage bl_ref before the charge accumulation phase. The opamp settles the bit-line voltage in advance during a precharge phase, so that when the actual MAC computation begins, the bit-line is already at the correct voltage level, eliminating settling delay during the computation phase
Solution Approach 2:
The patent segments the operation into distinct phases: a precharge phase where the bit-line is settled to bl_ref, and a charge accumulation phase where computation occurs. This temporal segmentation allows the opamp to perform settling operations separately from the computation operations, preventing settling delays from interfering with the MAC computation timing
3Ease of operation
If CG/SG charge coupling occurs during transitions, then flash cell switching is enabled, but errors in charge development phase are introduced
Solution Approach 1:
The patent introduces an intermediary mechanism by using a controlled pulse generator to mediate the SG line transitions. Instead of direct rail-to-rail switching, the pulse generator produces controlled pulses that activate the flash cell with minimal voltage swing and duration, thereby enabling flash cell switching while minimizing charge coupling to the bit-line and reducing errors in charge development
Solution Approach 2:
The patent uses periodic action by applying brief, periodic pulses to the SG line only when flash cell activation is required. These periodic pulses are synchronized with the charge accumulation timing, enabling flash cell switching at precise moments while minimizing the window for charge coupling errors to occur
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces errors in charge accumulation and sensing by controlling flash cell operations, improving the accuracy and efficiency of analog MAC systems in neural networks.
Implementation Method 1
The developed current on each flash cell in a column, while accessed, accumulates charges in a sense capacitor of the MAC system
Implementation Method 2
The bit-line settling time could be large due to undefined bit-line voltage in the previous phase and the parasitic capacitance on the bit-line
Data Source
AI summary
A matrix multiplication and addition (MAC) operating system is described where different cell currents flowing through different cells in a matrix for different PWM time intervals can be integrated and converted into a numeric value for the cumulative charge. The numeric value of the cumulative charge computed by the ADC is equivalent to MAC operations over multiplicity of cells. The operation is inherently error prone due to parasitic coupling effects from the switching of the memory cells in the array. The presented system minimizes the errors due to parasitic coupling through memory array.