Full-Analog Vector Matrix Multiplication Circuit
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Solution Overview
Problem
Existing processing-in-memory technologies face challenges in achieving high-precision vector matrix multiplication computations due to the need for frequent digital-to-analog and analog-to-digital conversions, which consume significant energy and area, and the immaturity of multi-value processes in resistive devices.
Innovation Solution
A full-analog-domain processing-in-memory circuit that performs vector matrix multiplication computations entirely in the analog domain using low-precision devices, eliminating the need for ADC and DAC conversions and implementing carry computations through an analog shift summation unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital-to-analog and analog-to-digital conversions are performed frequently in processing-in-memory, then computation precision is improved, but energy consumption and area usage increase exponentially
Solution Approach 1:
The patent extracts and removes the ADC and DAC conversion components from the processing-in-memory system. By performing vector matrix multiplication computations entirely in the analog domain using resistive devices to store weight values as conductance, the system eliminates the need for frequent digital-to-analog and analog-to-digital conversions between memory and computing units, thereby dramatically reducing energy consumption and area usage while maintaining computation precision through direct analog computation.
Solution Approach 2:
The patent substitutes the mechanical/digital conversion system (ADC/DAC) with a direct analog computation system. Instead of converting digital signals to analog and back, the system uses resistive devices to directly represent weight values as conductance and performs multiplication through analog current relationships, replacing the conversion mechanism with a native analog computation approach.
2Measurement precision
If multi-value processes are used in resistive devices for high-precision computation, then computation precision is improved, but manufacturing maturity deteriorates
Solution Approach 1:
The patent segments high-precision weight values into multiple binary bits, where each binary bit is represented by a separate resistive device. Instead of relying on multi-value processes to represent high-precision values directly, the system divides a high-precision weight value (e.g., 4-bit or more) into multiple binary components, each stored in a binary resistive device, thereby achieving high-precision computation through multiple low-precision devices while maintaining manufacturing maturity.
Solution Approach 2:
The patent changes the representation parameter of weight values from multi-value (analog or multi-level) to binary (two-state). By representing weight values as binary bits stored in resistive devices with mature binary processes, the system maintains manufacturing ease while achieving high-precision computation through the collective contribution of multiple binary devices representing different bit positions.
3Ease of manufacture
If low-precision devices are used to represent high-precision weight values, then manufacturing ease is improved, but computation precision deteriorates due to loss of information
Solution Approach 1:
The patent segments a high-precision weight value into multiple binary bits, with each bit represented by a separate low-precision resistive device. For example, a 4-bit weight value is divided into four binary bits, each stored in an individual binary device. This segmentation allows the system to use easy-to-manufacture binary devices while preserving the full precision of the original high-precision weight value through the combined representation of multiple segments.
Solution Approach 2:
The patent transitions from a single-dimension representation (one device per weight value) to a multi-dimensional representation (multiple devices per weight value, organized in array structures with row and column dimensions). By distributing the representation of a single high-precision weight value across multiple low-precision devices in a structured array, the system recovers the lost information dimension through spatial distribution and combinatorial encoding.
4Device complexity
If carry computations are performed in analog domain using low-precision devices, then device complexity is reduced, but maintaining computation precision becomes difficult
Solution Approach 1:
The patent performs preliminary organization of binary bits into structured array configurations before computation, with resistive devices arranged in rows and columns where weight values and input vectors are pre-positioned. This preliminary structuring enables systematic carry computation through the inherent analog current summation properties of the array, maintaining precision by ensuring proper weighting and alignment of binary contributions before the actual multiplication and summation operations.
Solution Approach 2:
The patent introduces the conductance of resistive devices as an intermediary to represent binary weight values. The conductance serves as a physical mediator that translates binary logical values into analog current relationships, enabling carry computations to be performed naturally through analog current summation while maintaining precision through the proportional relationship between conductance values and their corresponding binary weights.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces energy consumption and area usage while maintaining high computation precision, improving reliability and efficiency by directly performing carry computations in the analog domain.
Implementation Method 1
the device array consists of resistive devices, and is configured to store a weight value in a form of conductance and perform vector matrix multiplication computation on the analog input data and the weight value
Implementation Method 2
the output clamp circuit is configured to clamp an output point of the device array to a zero level, and convert a computation result in a form of current to an output result in a form of voltage
Data Source
AI summary
A full-analog vector matrix multiplication process-in-memory circuit comprises: an input circuit, a device array, an output clamping circuit, and an analog shift-and-add unit. The input circuit is used for sampling and holding analog input data and inputting the sampled analog input data into an array. The device array consists of resistive devices and is used for storing a weight value in the form of conductance and performing vector matrix multiplication calculation on the analog input data and the weight value. The output clamping circuit is used for clamping an output point of the device array to a zero level and converting a calculation result in the form of current into a result in the form of voltage for output. The analog shift-and-add unit is used for shifting and adding calculation results of devices in columns of the device array to complete carry calculation.