Analog Memory Charge Loss Compensation

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Solution Overview

Problem

Traditional solid-state memory devices face inefficiencies in program and read operations due to their binary nature, which becomes cumbersome as more bits are stored on each multi-level cell, leading to longer operation times and storage capacity limitations compared to mechanical hard disk drives.

Innovation Solution

The memory devices utilize analog signals to represent complete bit patterns across a continuum of threshold voltages, allowing for single read or write operations to store and retrieve multiple bits, rather than discrete binary operations, and incorporate sample and hold circuitry for efficient data handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If binary operations are used for each bit stored on multi-level cells, then data storage capacity increases, but operation time increases and efficiency decreases

Engineering Contradiction:
Improvestorage capacityVSAvoidoperation time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent combines multiple binary operations into a single analog operation by representing multiple bits as a continuous voltage level. Instead of performing separate read/write operations for each bit, the system performs one operation that simultaneously handles all bits stored in a multi-level cell, thereby reducing operation time while maintaining high storage capacity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the operational parameter from discrete binary states to continuous analog voltage levels. By storing data as specific voltage levels within a range rather than discrete 0s and 1s, the system enables single operations to represent multiple bits, significantly improving operational efficiency while preserving high storage density

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If binary operations are used for each bit stored on multi-level cells, then data storage capacity increases, but the number of operations required increases

Engineering Contradiction:
Improvestorage capacityVSAvoidoperational efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent merges multiple discrete binary operations into a single analog operation. By representing multiple bits as a continuous voltage level, the system performs one read or write operation that simultaneously handles all bits stored in a multi-level cell, thereby improving productivity without sacrificing storage capacity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The analog operation performed on multi-level cells serves multiple functions simultaneously - it can read, write, or verify multiple bits in a single operation cycle. This multi-functionality enhances productivity by eliminating the need for separate operations for each bit while maintaining high storage capacity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8174887B2Adjusting for charge loss in a memory
Publication Date: 2012.05.08 MICRON TECHNOLOGY INC
  • US8174887B2 patent drawing
  • US8174887B2 patent drawing
  • US8174887B2 patent drawing

AI summary

Memory and methods of operating a memory adjusting an output voltage of an analog storage device, such as a data cache capacitor holding a voltage level representative of data, in response to an estimated charge loss are useful for compensating for the effects of charge leakage from the analog storage devices.