Analog Memory Conductance Range Optimization
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Solution Overview
Problem
Analog memory devices face challenges in optimizing conductance ranges, leading to errors and reduced accuracy due to output currents residing in non-linear and saturation regions, which conventional techniques like bit slicing and hardware-aware retraining struggle to address effectively.
Innovation Solution
A method and system for optimizing conductance ranges of unit cells in analog memory devices by defining initial conductance ranges, encoding parameter values in a circuit model, and determining optimal ranges based on output current distributions, using techniques such as kernel density estimation and objective-based optimization to constrain output currents within linear regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional techniques like bit slicing and hardware-aware retraining are used, then device complexity is maintained, but measurement precision and manufacturing precision deteriorate due to output currents residing in non-linear and saturation regions
Solution Approach 1:
The patent applies preliminary action by determining optimal conductance ranges before actual operations are performed. The system uses a circuit model to simulate and analyze output current distributions, then pre-determines the optimal conductance ranges that will keep currents in linear regions during subsequent operations. This upfront optimization eliminates the need for complex runtime adjustments while maintaining high accuracy.
Solution Approach 2:
The patent uses copying by creating and analyzing a circuit model that replicates the behavior of the actual analog memory device. Instead of directly modifying the complex hardware to achieve optimal performance, the system creates a simplified digital copy (circuit model) to perform simulations and determine optimal parameters, then applies these parameters to the actual device. This avoids increasing physical device complexity while improving precision.
2Measurement precision
If conductance ranges are optimized to constrain output currents within linear regions, then measurement precision improves, but device complexity increases due to additional optimization processes
Solution Approach 1:
The patent replaces mechanical/system-level hardware modifications with computational analysis. Instead of physically adjusting or redesigning the analog memory device structure to optimize performance, the system uses software-based circuit modeling and simulation to determine optimal conductance ranges. This substitution of computational methods for physical modifications improves accuracy without increasing actual device complexity.
3Manufacturing precision
If initial conductance ranges are defined per column and optimized based on output current distribution, then manufacturing precision improves, but loss of time increases due to additional optimization steps
Solution Approach 1:
The optimization process is performed in advance during system initialization or configuration, before actual computational workloads are executed. By determining optimal conductance ranges beforehand using circuit model simulations, the system eliminates the need for repeated optimization during operations, thus minimizing time loss while maintaining high manufacturing precision.
Solution Approach 2:
The patent segments the optimization process by defining initial conductance ranges per column of unit cells rather than attempting to optimize the entire device uniformly. This column-level segmentation allows for more targeted and efficient optimization, reducing the overall computational burden and time required while improving precision for each specific column based on its unique characteristics.
Data Source
AI summary
Systems and methods for optimizing conductance ranges of a plurality of unit cells are described. A processor can define a plurality of initial conductance ranges for a plurality of unit cells arranged in a crossbar arrangement. The plurality of unit cells can include non-volatile memory (NVM) devices. An initial conductance range is defined per column of unit cells in the crossbar arrangement. The processor can use the plurality of initial conductance ranges to encode parameter values in a circuit model of the analog memory device. The processor can input a plurality of sample inputs into the circuit model to determine an output current distribution correlated to a plurality of products between the plurality of sample inputs and the parameter values. The processor can determine, based on at least one property of the output current distribution, an optimal conductance range for the plurality of unit cells.