Analog Neural Memory Arrays With Constant-Impedance Synapses
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Solution Overview
Problem
Existing artificial neural networks face challenges in achieving high computational parallelism and energy efficiency due to the lack of adequate hardware technology, particularly in implementing synapses that are bulky and inefficient compared to biological networks.
Innovation Solution
Utilizing non-volatile memory arrays as synapses in analog neural networks, where each memory cell has a constant source impedance and power consumption, enabling adaptive weight mapping for optimal performance in power and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital supercomputers or specialized graphics processing unit clusters are used to achieve high computational parallelism, then computational capability is improved, but energy efficiency deteriorates
Solution Approach 1:
The patent merges memory and computation functions into a single integrated structure. Memory cells store weights while simultaneously performing multiply-accumulate operations, eliminating the need for separate multiplication and addition logic circuits. This combination enables high computational parallelism while reducing energy consumption by avoiding data movement between separate memory and processing units.
Solution Approach 2:
The patent replaces traditional digital computation mechanisms with analog computing using memory cell currents. Instead of using digital logic circuits for multiplication and addition, the system uses the natural electrical properties of memory cells to perform computations directly, significantly improving energy efficiency while maintaining high computational parallelism.
2Measurement precision
If separate multiplication and addition logic circuits are used, then computational accuracy is improved, but device complexity increases
Solution Approach 1:
The patent combines multiplication and addition operations into a single integrated process within the memory array. The multiply-accumulate operation is performed simultaneously using memory cell currents, eliminating the need for separate multiplication and addition logic circuits. This reduces device complexity while maintaining computational accuracy through the inherent precision of analog current summation.
3Adaptability or versatility
If memory cells have variable source impedance, then adaptability is improved, but noise susceptibility increases
Solution Approach 1:
The patent implements substantially constant source impedance across all memory cells in the array through adaptive weight mapping. By distributing weights adaptively across the memory array and using techniques such as dummy bit lines and impedance matching circuits, the system maintains uniform source impedance characteristics. This homogeneity reduces noise susceptibility while preserving operational flexibility through the ability to programmably set individual cell weights.
Data Source
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AI summary
Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.