Error Array Significance Assessment in Analog Memory Arrays

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In multi-layered computational processes, such as neural networks, existing systems face challenges in efficiently determining and mitigating error values, particularly in analog memory arrays where errors can worsen with age and usage, affecting the accuracy of data flow processes.

Innovation Solution

A computer system that utilizes multiple analog memory arrays to determine the significance of error values by creating an error array data structure, assessing each node's significance, and implementing remedial operations, such as retraining, to mitigate errors, with error thresholds calibrated to account for hardware deterioration and input variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If analog memory arrays are used to implement multi-layer computational processes, then computational efficiency is improved, but error accumulation and hardware deterioration worsen over time

Engineering Contradiction:
Improvecomputational efficiencyVSAvoiderror accumulation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system performs preliminary error detection by generating error arrays that capture potential errors before they propagate through subsequent layers. By detecting and addressing errors at their source in earlier layers, the system prevents error accumulation in later layers, thus maintaining reliability while preserving computational efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where error information from error arrays is fed back into the computational process. This feedback enables the system to identify significant errors, adjust computations, and mitigate their impact, thereby maintaining high reliability without sacrificing the computational efficiency provided by analog memory arrays.

Inventive Principle:
Principle #23Feedback

2Reliability

If error detection and mitigation operations are performed at each layer, then reliability is improved, but computational overhead and processing time increase

Engineering Contradiction:
Improveerror mitigationVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system applies local quality by performing error detection and mitigation only where necessary. Instead of uniformly processing all error values, the system identifies significant errors in specific layers and focuses remedial operations on those locations, thereby improving reliability without incurring excessive computational overhead across the entire system.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system employs partial action by selectively applying error mitigation operations only to significant errors rather than all errors. By using significance thresholds to filter which errors require remediation, the system achieves adequate reliability while minimizing the time and computational resources spent on error handling.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If significance thresholds are calibrated to account for hardware deterioration, then reliability is improved, but system complexity increases

Engineering Contradiction:
Improvethreshold calibrationVSAvoidcalibration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system manages complexity by dynamically adjusting significance thresholds based on observed error patterns and hardware deterioration. Rather than implementing complex predictive models, the system adapts thresholds to current system state, maintaining high reliability while keeping the calibration mechanism relatively simple and manageable.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11294763B2Determining significance levels of error values in processes that include multiple layers
Publication Date: 2022.04.05 HEWLETT PACKARD ENTERPRISE DEV LP
  • US11294763B2 patent drawing
  • US11294763B2 patent drawing
  • US11294763B2 patent drawing

AI summary

A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.