Analog Non-Volatile Memory Final Bake for Read Current Stability

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Solution Overview

Problem

Non-volatile memory devices face read current instabilities due to electron trap recharging at the gate oxide-channel interface, leading to random telegraph noise and threshold voltage shifts, which affect the accuracy of memory devices, especially those operated in analog or multilevel cell modes.

Innovation Solution

The method involves programming memory cells to a predetermined mid-program state before a final high temperature bake, stabilizing the read current by reducing threshold voltage shifts over time, thereby improving read operation accuracy and memory retention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If a final high temperature bake is performed after memory cells are programmed to various states, then memory retention is improved, but read current stability deteriorates due to electron trap recharging and threshold voltage shifts

Engineering Contradiction:
Improvememory retentionVSAvoidread current stability
Core Design Contradiction:
Duration of action of stationary objectVSReliability

Solution Approach 1:

The patent applies preliminary action by programming all memory cells to a predetermined mid-program state before performing the final high temperature bake. This preparatory step ensures that the memory cells are in a stable, uniform state that is less susceptible to electron trap recharging effects during the bake process, thereby maintaining read current stability while still achieving improved memory retention through the bake.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If memory cells are operated in analog or multilevel cell modes to increase storage capacity, then productivity is improved, but read current stability deteriorates due to increased sensitivity to threshold voltage shifts

Engineering Contradiction:
Improvestorage capacityVSAvoidread current stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies parameter changes by establishing a specific predetermined mid-program state as a reference point for all memory cells before the final bake. This standardized parameter setting creates a stable baseline that reduces variability in threshold voltage shifts during operation, thereby improving read current stability while maintaining the high storage capacity enabled by analog or multilevel cell modes.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces read current fluctuations and enhances the longevity of memory retention by stabilizing the read current and threshold voltage, improving the operational stability of non-volatile memory devices.

Implementation Method 1

subjecting the non-volatile memory device to a final high temperature bake

Methodology Applied
Scientific EffectThermal annealing: Annealing

Data Source

PatentEP4026127B1Method of improving read current stability in analog non-volatile memory using final bake in predetermined program state
Publication Date: 2024.01.24 SILICON STORAGE TECHNOLOGY INC
  • EP4026127B1 patent drawingFigure 1
  • EP4026127B1 patent drawingFigure 2
  • EP4026127B1 patent drawingFigure 3

AI summary

A method of improving stability of a memory device having a controller configured to program each of a plurality of non-volatile memory cells within a range of programming states bounded by a minimum program state and a maximum program state. The method includes testing the memory cells to confirm the memory cells are operational, programming each of the memory cells to a mid-program state, and baking the memory device at a high temperature while the memory cells are programmed to the mid-program state. Each memory cell has a first threshold voltage when programmed in the minimum program state, a second threshold voltage when programmed in the maximum program state, and a third threshold voltage when programmed in the mid-program state. The third threshold voltage is substantially at a mid-point between the first and second threshold voltages, and corresponds to a substantially logarithmic mid-point of read currents.