Analog In-Memory MAC Circuit for Multibit Neural Computing
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Solution Overview
Problem
Conventional computation architectures face challenges in integrating MAC operation units with memory units due to a significant imbalance in transistor count, leading to high latency and energy consumption, particularly in neural network applications.
Innovation Solution
An in-memory computing architecture that integrates a MAC unit with memory cells using analog computing methods, employing a C-2C ladder-based analog MAC unit for multibit operations, reducing the transistor count disparity and enhancing performance by minimizing data fetches and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a digital MAC unit is integrated with memory cells, then computing performance is improved, but the transistor count ratio becomes unbalanced making integration difficult
Solution Approach 1:
The patent merges the MAC unit with memory cells by sharing transistor resources. The MAC unit is implemented using the same memory cell transistors that store data, eliminating the need for separate dedicated transistors for MAC operations. This merging resolves the transistor count imbalance by making the MAC functionality utilize existing memory transistors rather than requiring additional ones.
Solution Approach 2:
The memory cell transistors are designed to serve multiple functions: data storage and MAC operations. By making the transistors universal, they can operate as storage elements during memory operations and as computing elements during MAC operations, thereby reducing the overall transistor count required while maintaining both memory and computing capabilities.
2Ease of manufacture
If memory units and processing units are physically separated, then device design is simplified, but data transfer latency and energy consumption increase
Solution Approach 1:
The patent combines memory units and processing units into a single integrated structure where MAC operations are performed within the memory array itself. This eliminates the physical separation between storage and processing, allowing data to be computed in-place without requiring data movement between separate units, thereby reducing latency and energy consumption.
Solution Approach 2:
The patent introduces an in-memory computing mechanism that acts as an intermediary between traditional memory and processing units. This intermediary layer performs MAC operations directly within the memory cells, bridging the gap between storage and computation and eliminating the need for data transfer between physically separated units.
3Ease of operation
If data is serially fetched from storage layer by layer, then memory access is simplified, but energy overhead and latency increase
Solution Approach 1:
The patent enables memory cells to perform MAC operations on data while it is stored, without requiring external processing units to fetch and process the data. The memory cells themselves serve their stored data, performing computations in-place and eliminating the energy overhead associated with serial data fetching and processing.
Solution Approach 2:
The patent performs MAC operations preliminary within the memory cells before data needs to be transferred out. By pre-computing results within the storage location, the system eliminates the need for subsequent data fetching and processing steps, thereby reducing energy overhead and latency.
Data Source
AI summary
Systems, apparatuses and methods include technology that receives, with a first plurality of multipliers of a multiply-accumulator (MAC), first digital signals from a memory array, wherein the first plurality of multipliers includes a plurality of capacitors. The technology further executes, with the first plurality of multipliers, multibit computation operations with the plurality of capacitors based on the first digital signals, and generates, with the first plurality of multipliers, a first analog signal based on the multibit computation operations.