Analog Memory Segmented Discharge Lines for Parasitic Capacitance
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Solution Overview
Problem
Conventional analog memories in Y/C separation circuits suffer from significant parasitic capacitance in discharge lines, leading to errors between input and output signals due to the large number of switched capacitor portions connected to a single discharge line, especially when handling composite signals with high chrominance frequencies.
Innovation Solution
The analog memory design incorporates multiple discharge lines, allowing only one memory block to discharge at a time while the others are disconnected from the buffer circuit, reducing the number of second switching elements connected to each line and minimizing parasitic capacitance, thereby preventing signal distortion during line switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple switched capacitor portions are connected to a single discharge line, then the device complexity is reduced, but the parasitic capacitance in the discharge line increases significantly
Solution Approach 1:
The patent divides the single discharge line into multiple discharge lines, with each discharge line serving a specific memory block. This segmentation reduces the number of switched capacitor portions connected to each discharge line, thereby minimizing parasitic capacitance while maintaining manageable device complexity through systematic organization of multiple discrete discharge paths
2Ease of manufacture
If all memory blocks discharge simultaneously to the same discharge line, then the manufacturing process is simplified, but signal distortion occurs due to parasitic capacitance effects
Solution Approach 1:
The patent assigns dedicated discharge lines to specific memory blocks, enabling selective discharge of individual memory blocks rather than simultaneous discharge of all blocks to a common line. This segmentation allows precise control over which memory block discharges when, preventing signal distortion caused by parasitic capacitance while maintaining manufacturing simplicity through standardized modular design
Solution Approach 2:
The patent implements dynamic control of discharge line connections, where the discharge line connection state changes based on which memory block is currently discharging. By dynamically switching which discharge line is active and connecting to the buffer circuit, the system prevents signal distortion while maintaining ease of manufacture through controlled temporal separation of discharge operations
3Device complexity
If the discharge line is connected to all second switching elements, then the device structure is simplified, but the parasitic capacitance causes large errors between input and output signals
Solution Approach 1:
The patent segments the discharge line connections by assigning dedicated discharge lines to specific memory blocks, so that not all second switching elements are connected to a single discharge line. This segmentation reduces the total parasitic capacitance in each discharge line while maintaining manageable connection structure through systematic one-to-one or one-to-few mappings between discharge lines and memory blocks
Solution Approach 2:
The patent introduces discharge line selection switches as intermediary components that control which discharge line is connected to the buffer circuit based on which memory block is currently discharging. This intermediary mechanism prevents parasitic capacitance from causing large signal errors while maintaining relatively simple overall connection structure by using controlled switching rather than permanent multi-point connections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces parasitic capacitance effects on the output signal, maintaining signal integrity even with increased numbers of switched capacitor portions, by dividing the discharge line into multiple lines and controlling connections to the operational amplifier, thus reducing errors and distortion.
Implementation Method 1
the capacitive element C1-C4 is configured to charge and discharges the electric charges corresponding to the input signal Vin
Implementation Method 2
the drain of each second MOS transistor Mout1-Mout4 is connected to the non-inverting input terminal of the operational amplifier OP
Data Source
AI summary
According to a preferred embodiment of the present invention, an analog memory includes a first to third memory blocks. Each of the first to third memory blocks includes a plurality of capacitive elements for storing electric charges corresponding to an input signal, an output line for transferring the electric charges, and a plurality of MOS transistors each for changing connection between the capacitive element and the output line. When a signal is outputted from the output line to a buffer circuit by sequentially connecting the capacitive element to the output line in the first memory block, all connections between the capacitive elements and the output line are disconnected in the second and third memory blocks with the output line of the first memory block and the output line of the second memory block connected.