Analog Neural Memory Arrays With Shared High-Voltage Blocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing analog neuromorphic memory systems for artificial neural networks require extensive circuitry outside the arrays, increasing space and power consumption, and lack efficient vector-by-matrix multiplication capabilities.
Innovation Solution
Analog neuromorphic memory systems utilizing CMOS technology and non-volatile memory arrays with vector-by-matrix multiplication arrays, shared high voltage generation, verify, and testing blocks, enabling in-situ computation and reducing external circuitry needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If extensive circuitry is provided outside the memory arrays to support both individual and array-wide read operations and provide wide range voltage and current levels, then the system can support both types of read operations, but the amount of space needed on the semiconductor die increases
Solution Approach 1:
The patent merges the high voltage generation circuitry into shared blocks that serve multiple vector-by-matrix multiplication arrays simultaneously. Instead of providing extensive circuitry outside each array, the high voltage generation blocks are consolidated and shared across arrays, reducing the total semiconductor die space while maintaining the capability to support both individual and array-wide read operations.
Solution Approach 2:
The shared high voltage generation blocks are designed to be universal components that can service multiple different arrays and support multiple types of operations (individual reads, array-wide reads, programming, erasing). This multi-functionality allows the system to maintain versatility in read operations while minimizing the space dedicated to support circuitry.
2Adaptability or versatility
If extensive circuitry outside the arrays is provided to provide wide range of voltage and current levels, then both read operations are supported, but power consumption increases
Solution Approach 1:
The patent consolidates high voltage generation into shared blocks that serve multiple arrays, eliminating redundant circuitry. By merging these power-intensive functions into shared resources, the system reduces overall power consumption while maintaining the ability to provide the wide range of voltage and current levels needed for both individual and array-wide read operations.
3Ease of manufacture
If CMOS analog circuits are used for artificial neural networks, then the system can be implemented with standard technology, but the synapses become too bulky given the high number of neurons and synapses
Solution Approach 1:
The patent replaces traditional bulky CMOS analog circuit implementations with a memory-based approach using non-volatile memory cells (such as flash memory) to implement synapse functionality. This substitution uses the memory cell's ability to store charge states to represent synaptic weights, dramatically reducing the area required per synapse while maintaining CMOS compatibility through standard memory fabrication processes.
Solution Approach 2:
The invention changes the fundamental parameter representation from analog voltage levels in traditional CMOS circuits to charge storage states in memory cells. By utilizing the memory cell's threshold voltage and charge retention properties, the system achieves synapse functionality with much smaller device dimensions, enabling high-density neural network implementations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution minimizes external circuitry requirements, enhances energy efficiency, and supports both individual and array-wide read operations, optimizing hardware for deep learning neural networks.
Implementation Method 1
each of the memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate
Implementation Method 2
The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. The analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication arrays and various components shared by those arrays. The shared components include high voltage generation blocks, verify blocks, and testing blocks. The analog neuromorphic memory system optionally is used within a long short term memory system or a gated recurrent unit system.