Multi-Level Analog Memory Cell Programming for Time-Gap Errors
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Solution Overview
Problem
Multi-level analog memory cells face errors during data reconstruction due to time gaps between programming pages, leading to reduced programming accuracy and speed, as existing methods rely on reconstructing previous data which introduces error probability and requires large margins between programming levels.
Innovation Solution
The Memory Signal Processor identifies Discontinuous Programming scenarios and selects appropriate storage strategies, such as modifying programming parameters or using cached data to compute new programming levels, reducing error probability and increasing programming speed by relaxing accuracy requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in multi-level analog memory cells with time gaps between programming pages, then storage capacity is increased, but error probability increases due to data degradation over time
Solution Approach 1:
The system performs preliminary actions by caching previously programmed data in buffers before programming subsequent pages. This allows the programming process to proceed without reading back degraded data from memory cells, preventing error accumulation while maintaining high storage capacity through multi-level cell programming
Solution Approach 2:
Buffers serve as intermediary storage between the memory cells and the programming process. Instead of directly reading degraded data from cells and writing new pages, the system uses buffers to hold previously programmed data, eliminating the need to read degraded data and thereby reducing error probability while maintaining storage capacity
2Reliability
If large margins are used between programming levels to account for errors, then reliability is improved, but programming precision requirements increase
Solution Approach 1:
By caching previously programmed data in buffers before programming new pages, the system eliminates the need to read back data from memory cells. This preliminary action prevents error accumulation and allows the use of smaller margins between programming levels, reducing precision requirements while maintaining reliability
Solution Approach 2:
The system implements a feedback mechanism where previously programmed data is cached and used to determine subsequent programming operations. This feedback loop allows the system to maintain accuracy with smaller margins by using the cached data as a reference, rather than relying on large margins to compensate for read errors
3Reliability
If data is read and reconstructed from memory cells before programming new pages, then data integrity is maintained, but programming speed decreases due to additional read operations
Solution Approach 1:
The system performs preliminary caching of previously programmed data in buffers before initiating new programming operations. This preliminary action eliminates the need for read-reconstruct-write cycles during page programming, maintaining data integrity through the cached reference while significantly improving programming speed by removing redundant read operations
Solution Approach 2:
By maintaining cached data in buffers throughout the programming process, the system enables continuous programming operations without interruption for read verification. The cached data provides continuous reference information needed for accurate programming, allowing the useful action of programming to proceed continuously at high speed without breaking for read operations
Data Source
AI summary
A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.