Multi-Level Analog Memory Cell Programming Across Time Gaps

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Solution Overview

Problem

Multi-level analog memory cells face errors during data reconstruction due to time gaps between programming pages, leading to reduced programming accuracy and speed, as existing methods rely on reconstructing previous data which introduces error probability and requires accounting for potential errors by reducing programming speed or storage capacity.

Innovation Solution

The Memory Signal Processor identifies Discontinuous Programming scenarios and selects appropriate storage strategies, such as modifying programming parameters or using cached data to compute new programming levels, reducing error probability and increasing programming speed by relaxing accuracy requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is stored in multi-level analog memory cells with time gaps between programming pages, then storage capacity is improved, but error probability increases due to data degradation over time

Engineering Contradiction:
Improvestorage capacityVSAvoiderror probability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The system performs preliminary actions by detecting time gaps between programming operations and proactively selecting appropriate storage strategies before errors occur. The memory controller monitors programming timestamps and preemptively adjusts programming parameters or retrieves cached data to prevent data degradation errors.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms by continuously monitoring the time intervals between programming operations and using this information to dynamically adjust storage strategies. The memory controller receives feedback about time gaps and automatically selects optimal programming parameters or cached data retrieval to maintain data integrity.

Inventive Principle:
Principle #23Feedback

2Reliability

If conventional reconstruction methods are used to account for potential errors, then reliability is improved, but programming speed decreases

Engineering Contradiction:
Improveprogramming accuracyVSAvoidprogramming speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system applies dynamic programming by adjusting programming parameters in real-time based on detected time gaps. When time gaps are detected, the system dynamically modifies programming strategies such as using cached data or adjusting programming pulses, allowing programming speed to be optimized for each specific scenario rather than using fixed conservative parameters.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes programming parameters based on time gap detection. When time gaps between programming operations are detected, the memory controller modifies programming parameters such as pulse width, voltage levels, or retrieves previously cached programming data to compensate for potential degradation without requiring overly conservative programming that would slow down the process.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If conservative programming parameters are used to account for data degradation, then error probability is reduced, but programming speed decreases

Engineering Contradiction:
Improveerror probabilityVSAvoidprogramming speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The system performs preliminary detection of time gaps between programming operations and takes proactive measures before data degradation occurs. By detecting the time gap early, the system can retrieve cached programming data or adjust parameters in advance, avoiding the need for slow conservative programming while still preventing errors.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8681549B2Programming schemes for multi-level analog memory cells
Publication Date: 2014.03.25 APPLE INC
  • US8681549B2 patent drawing
  • US8681549B2 patent drawing
  • US8681549B2 patent drawing

AI summary

A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.