Analog Memory Architecture for Zero-Value Shifting

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Solution Overview

Problem

Current memory architectures for neural networks face challenges in efficiently implementing zero-value shifting and differential reading, which are crucial for neural network training processes like backpropagation, especially in achieving symmetry point convergence and handling positive and non-positive weights.

Innovation Solution

An analog memory architecture with a weight array and a reference array, utilizing cross-point devices and differential unipolar switching memory devices, enables zero-value shifting by applying voltage pulses and copying conductance values to achieve symmetry point convergence and represent both positive and non-positive weights through double differential reading.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional memory architectures are used for neural network training, then computational tasks can be performed, but efficiency is insufficient and zero-value shifting cannot be achieved

Engineering Contradiction:
Improvetraining efficiencyVSAvoidarchitecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory architecture is segmented into a weight array for storing neural network weights and a reference array for storing reference values. This segmentation enables independent optimization of each array's function, allowing efficient zero-value shifting through differential reading while maintaining manageable complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A differential reading mechanism is introduced as an intermediary between the weight array and readout circuitry. This intermediary performs differential comparisons that enable zero-value shifting capability without requiring complex modifications to the base memory cells, thus improving productivity while controlling complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If symmetry point convergence is implemented, then weight representation accuracy is improved, but additional computational steps are required

Engineering Contradiction:
Improveweight representation accuracyVSAvoidconvergence time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The architecture pre-establishes symmetry points during initialization and maintains them throughout training operations. By preparing the reference array with pre-computed reference values corresponding to symmetry points, the system achieves accurate weight representation without requiring iterative convergence steps during forward propagation, thus improving precision without time penalty

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The reference array stores copied reference values that represent symmetry points. These pre-copied reference values enable direct comparison with weight array values to achieve accurate weight representation, eliminating the need for repeated convergence computations and reducing time loss

Inventive Principle:
Principle #26Copying

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This architecture accelerates neural network training by enabling efficient zero-value shifting and differential reading, improving performance over traditional CPU and GPU computational methods through parallel computations and optimized weight representation.

Implementation Method 1

The second cross-point devices include differential unipolar switching memory devices configured to enable zero-value shifting of the outputs of the first cross-point devices

Methodology Applied
Scientific EffectConductance: Conduction (electrical)

Data Source

PatentUS10832773B1Architecture for enabling zero value shifting
Publication Date: 2020.11.10 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10832773B1 patent drawing
  • US10832773B1 patent drawing
  • US10832773B1 patent drawing

AI summary

A system includes an analog memory architecture for performing differential reading. The analog memory architecture includes a weight array including first cross-point devices located at intersections of a first set of conductive column wires and a first set of conductive row wires, and a reference array operatively coupled to the weight array and including second cross-point devices located at intersections of a second set of conductive column wires and a second set of conductive row wires. The second cross-point devices include differential unipolar switching memory devices configured to enable zero-value shifting of the outputs of the first cross-point devices.