Digital Calibration Nodes for Analog ML Accelerator Accuracy
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Solution Overview
Problem
Analog circuits used in machine learning accelerators face issues such as digital-to-analog conversion offset, amplifier distortion, and errors in gain and voltage, leading to inaccuracies in neural network computations.
Innovation Solution
An error calibration method and apparatus that utilize a digital circuit to detect and minimize errors by generating a calibration node at the next layer of the neural network's operational layers, achieved through a processor and memory system, which compensates for errors in the analog circuit's computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If analog circuits are used to achieve neural network computations, then computation speed and energy efficiency are improved, but accuracy deteriorates due to DAC offset, amplifier distortion, and gain/voltage errors
Solution Approach 1:
The patent introduces a calibration node as an intermediary element between the analog computing layers. This calibration node captures the error propagated from previous layers and uses it to generate correction values that are fed back into the analog circuit, thereby mediating between the analog computation and the desired accuracy without replacing the analog architecture
Solution Approach 2:
The patent implements a feedback mechanism where the calibration node receives error information from the output of analog computing layers, processes this error through digital circuits to generate correction values, and feeds these corrections back to minimize the error in subsequent computations. This closed-loop feedback system continuously reduces the impact of analog circuit errors
2Use of energy by moving object
If analog circuits are used for neural network computations, then energy consumption is reduced, but error rate increases due to inherent analog circuit imperfections
Solution Approach 1:
The calibration node serves as a mediator that separates the analog computation path (energy-efficient) from the error correction path. It captures errors from analog computations and generates digital correction values without requiring full digital reconstruction of the computation, thus maintaining energy efficiency while improving reliability
Solution Approach 2:
The patent selectively replaces only the error correction and calibration functions with digital circuits, while maintaining analog circuits for the core neural network computations. This partial substitution approach improves reliability by eliminating analog errors in the correction path while preserving the energy efficiency of analog computation in the main processing path
Data Source
AI summary
An error calibration apparatus and method are provided. The method is adapted for calibrating a machine learning (ML) accelerator. The ML accelerator achieves computation by using an analog circuit. An error between an output value of one or more computing layers of a neural network and a corresponding corrected value is determined. The computation of the computing layers is achieved by the analog circuit. A calibration node is generated according to the error. The calibration node is located at the next layer of the computing layers. The calibration node is used to minimize the error. The calibration node is achieved by a digital circuit. Accordingly, error and distortion of the analog circuit could be reduced.