Analog Model Equivalence Checking via Waveform Mapping
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Solution Overview
Problem
The complexity of semiconductor integrated circuit designs poses challenges in design verification, particularly in verifying the interface between analog and digital blocks, as accurate SPICE netlists are not available until late in the design cycle, leading to bottlenecks and compromised functional verification.
Innovation Solution
The approach involves using a common input stimulus to generate output waveforms from both high-level and low-level representations of a semiconductor circuit, allowing for equivalence checking between different representations, such as SPICE netlists and SystemVerilog models, to ensure accuracy and reduce simulation run times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If SPICE netlists are used for accurate analog circuit simulation, then measurement precision of circuit behavior is improved, but device complexity and development time increase due to late availability
Solution Approach 1:
The patent creates a simplified copy of the circuit model (first circuit model) that can be simulated early in the design cycle before detailed SPICE netlists are available. This copy is later verified against the detailed model (second circuit model) to ensure accuracy, allowing early verification without waiting for complete detailed models.
Solution Approach 2:
The patent performs preliminary simulation and verification using simplified circuit models before the detailed SPICE netlists are ready. By conducting equivalence checking early in the design cycle, the patent enables early detection of design issues without waiting for late-stage detailed modeling.
2Manufacturing precision
If detailed low-level circuit models are used for verification, then manufacturing precision of design verification is improved, but device complexity increases
Solution Approach 1:
The patent segments the verification process into two stages: first using simplified circuit models for initial verification, then using detailed SPICE netlists for final verification. This segmentation allows the system to handle complexity in manageable portions rather than requiring all detailed models to be available simultaneously.
Solution Approach 2:
The patent introduces an intermediary verification process that compares simplified models against detailed models. This intermediary equivalence checking mechanism allows detailed verification without requiring the detailed models to be used throughout the entire design cycle, reducing overall complexity.
3Productivity
If high-level models are used early in design cycle, then productivity of design verification is improved, but measurement precision deteriorates
Solution Approach 1:
The patent maintains continuous verification through multiple stages: initial verification with simplified models, followed by equivalence checking against detailed models. This continuous multi-stage verification ensures that productivity gains from early simplified modeling do not compromise final verification accuracy.
Solution Approach 2:
The patent implements feedback through equivalence checking, where the detailed circuit model is used to verify and validate the simplified model. This feedback mechanism ensures that the simplified models used for high-speed verification maintain accuracy by being validated against the detailed reference model.
Data Source
AI summary
Techniques for equivalence checking of analog models are disclosed. The models include transistor level representations. The representations are used for simulation and verification of the circuit and are required to give similar output results in response to a given input stimulus. A common input stimulus is created for a first representation and a second representation of a semiconductor circuit. Output waveforms are generated for the first representation and the second representation using the common input stimulus. The first output waveforms and the second output waveforms are checked for equivalence. Signals from the first output waveforms are mapped to the second output waveforms.