Analog Multiplexing for Decision Feedback Equalizer Bias Precision

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Solution Overview

Problem

Conventional distortion correction techniques in semiconductor memory devices, particularly decision feedback equalizers (DFE), face challenges in generating precise bias levels across varying process, voltage, and temperature (PVT) conditions, leading to inefficiencies in channel equalization and increased data errors due to inter-symbol interference.

Innovation Solution

An analog multiplexing scheme is employed to efficiently route and select bias levels for DFE circuits, using a multi-level bias generator and multiplexer to deliver precise bias levels across different channels and taps, ensuring accurate distortion correction despite PVT variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional bias level generation methods are used in DFE circuits, then the device complexity is reduced, but the manufacturing precision and reliability of bias levels across PVT conditions deteriorate

Engineering Contradiction:
Improvebias level precisionVSAvoidbias generation circuit complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Multiple bias levels are generated using a single bias generator circuit through analog multiplexing, combining the functions of what would traditionally require multiple separate bias generation circuits. This reduces device complexity while maintaining precision across PVT conditions.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bias generator is designed to provide multiple bias levels (e.g., VB1, VB2, VB3) for different channels and taps through a single multi-functional circuit that can be selectively configured, making the bias generation system universal rather than requiring dedicated circuits for each bias level.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If separate bias levels are generated for each channel, then the adaptability to different channel conditions is improved, but the device complexity and routing resources increase

Engineering Contradiction:
Improvechannel-specific bias adaptationVSAvoidrouting complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

An analog multiplexer acts as an intermediary between the single bias generator and multiple DFE channels, selectively routing the appropriate bias level to each channel based on its specific distortion characteristics. This provides channel-specific adaptation without requiring separate bias generators for each channel.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The bias level assignment is dynamically configurable through programming, allowing the system to adapt to different channel conditions and distortion characteristics. The multiplexer can be programmed to route different bias levels to different channels based on measured or predetermined channel qualities.

Inventive Principle:
Principle #15Dynamics

3Productivity

If the number of channels is increased, then the productivity and data throughput are improved, but the resources and time for routing bias levels increase

Engineering Contradiction:
Improvedata throughputVSAvoidbias routing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

Multiple bias level routing operations are merged into a single analog multiplexer that can efficiently switch between different bias levels for multiple channels. This consolidates the routing infrastructure, reducing the time and resources required compared to separate routing paths for each channel.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10785067B2Analog multiplexing scheme for decision feedback equalizers
Publication Date: 2020.09.22 MICRON TECHNOLOGY INC
  • US10785067B2 patent drawing
  • US10785067B2 patent drawing
  • US10785067B2 patent drawing

AI summary

A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.