Analog Vector Multiplier Compression for Shared Neural Matrices
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Solution Overview
Problem
Existing neural networks that implement ensembles of multiple models face significant challenges in terms of memory requirements, energy consumption, and processing time, which are multiplied by the number of models used.
Innovation Solution
An analog vector multiplier circuit and crossbar array circuit are employed to perform parallel multiply and accumulate operations, utilizing programmable resistive elements and transistors to reduce the memory and energy demands by sharing a single shared matrix across multiple models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple models are implemented for ensemble neural networks, then classification accuracy and uncertainty calibration are improved, but memory requirements and energy consumption are multiplied by the number of models
Solution Approach 1:
The patent merges multiple model computations into a single neural network by sharing common weight matrices across different model instances. The circuit architecture allows multiple models to coexist by multiplexing shared resources (weight matrices, activation functions) across time or space, so that K models do not require K times the resources of a single model. This resolving the contradiction between ensemble accuracy and resource consumption.
Solution Approach 2:
The neural network implements multi-functionality by enabling a single network to perform computations for multiple different models sequentially or in parallel through shared weight matrices. The same circuit infrastructure supports K different models by dynamically reconfiguring which weight matrices are active, allowing one universal network to replace K dedicated networks.
2Reliability
If multiple models are implemented for ensemble neural networks, then classification accuracy and uncertainty calibration are improved, but processing time is multiplied by the number of models
Solution Approach 1:
The patent segments the computation by separating the shared weight matrix multiplication from the model-specific computations. By factoring out common operations (shared weight matrices) and only computing model-specific portions when needed, the processing time is reduced from O(K) to O(1) for the shared parts, achieving faster inference while maintaining ensemble accuracy.
Solution Approach 2:
The shared weight matrices are pre-computed and stored in the neural network, so that during inference only the model-specific computations need to be performed. This preliminary preparation of common resources eliminates the need to recompute shared operations for each model, significantly reducing processing time while maintaining the benefits of ensemble methods.
3Reliability
If multiple models are implemented for ensemble neural networks, then classification accuracy and uncertainty calibration are improved, but memory requirements are multiplied by the number of models
Solution Approach 1:
The patent merges the storage requirements of K models into a single network by sharing common weight matrices. Instead of storing K separate sets of weights, the system stores one set of shared weight matrices that can be reused across all K models, reducing memory requirements from O(K) to O(1) while maintaining the computational capabilities of the ensemble.
Solution Approach 2:
The neural network achieves universality by designing a single network architecture that can compute outputs for multiple different models through shared weight matrices. This multi-functional design allows one network to serve K models without requiring K times the memory, as the same memory resources are reused for different model computations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces memory storage and energy consumption while maintaining classification accuracy, by using an analog vector multiplier circuit and crossbar array to perform parallel operations efficiently.
Implementation Method 1
a first programmable resistive element programmed to have a first resistance representative of the first value
Implementation Method 2
a first current mirror configured to apply a current generated based on the third value to the branch selected by the control circuit in order to generate, across the selected branch, a first voltage proportional to the result of the first multiplication
Data Source
Figure 1~2A
Figure 2B
Figure 3
AI summary
The present disclosure relates to an analog vector multiplier circuit comprising a first circuit comprising: - a first branch comprising the series connection of a first programmable resistive element and a first transistor; - a second branch comprising the series connection of a second programmable resistive element and a second transistor; - a control circuit configured to control the first and second transistors to select the first or second branch; and - a first current mirror configured to apply a current generated to the branch selected by the control circuit in order to generate a first voltage.