Analog Multiply-Accumulate Circuit for High-Speed Neural Network Processing
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Solution Overview
Problem
Existing analog-type circuits for multiply-accumulate operations in neural networks are complex and do not facilitate high-speed arithmetic processing.
Innovation Solution
The proposed arithmetic apparatus includes multiple input line pairs and multiply-accumulate devices with multiplication units, an accumulation unit, a charging unit, and an output unit, which generate and accumulate positive and negative weight charges, and perform threshold determination using a common threshold value to simplify circuit configuration and enable high-speed processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If analog-type circuits are used for multiply-accumulate operations, then power consumption is reduced, but circuit configuration becomes complex
Solution Approach 1:
The analog circuit is divided into multiple independent multiply-accumulate devices, each handling specific neurons or operations. This segmentation allows parallel processing while maintaining simplified individual device structures, resolving the contradiction between power efficiency and circuit complexity.
Solution Approach 2:
Each multiply-accumulate device is designed as a universal unit capable of performing the same multiply-accumulate operation for different neurons. This multi-functionality reduces overall circuit complexity by using identical standardized blocks rather than custom circuits for each neuron, while maintaining low power consumption through analog operation.
2Use of energy by moving object
If analog-type circuits are used for multiply-accumulate operations, then power consumption is reduced, but arithmetic operation speed is limited
Solution Approach 1:
The system is segmented into multiple parallel multiply-accumulate devices that operate simultaneously. This parallelization increases overall arithmetic operation speed while each individual device maintains low power consumption through analog operation, resolving the contradiction between power efficiency and processing speed.
Solution Approach 2:
The analog multiply-accumulate devices perform continuous arithmetic operations without the discrete switching cycles required by digital systems. This continuous operation enables high-speed processing while maintaining low power consumption, as the analog circuits operate in their optimal regime without frequent state transitions.
3Measurement precision
If separate integration circuits are used to combine arithmetic operation results, then calculation accuracy is improved, but circuit configuration becomes more complex
Solution Approach 1:
The multiplication and accumulation functions are merged into a single integrated multiply-accumulate device. This combining eliminates the need for separate integration circuits while maintaining calculation accuracy through careful analog circuit design, resolving the contradiction between precision and complexity.
Solution Approach 2:
The multiply-accumulate device is designed as a universal unit that inherently performs both multiplication and accumulation operations in an integrated manner. This multi-functionality eliminates the need for additional separate integration circuits, reducing overall circuit complexity while preserving computational accuracy through unified analog processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration simplifies the circuit and enables high-speed arithmetic operation processing by omitting the need for integrating arithmetic operation results into a single signal, allowing all multiply-accumulate devices to operate at the same timing and reducing power consumption.
Implementation Method 1
The plurality of multiplication units is respectively connected to at least some of the plurality of input line pairs and is capable of generating each of a positive weight charge corresponding to a positive weight product value obtained by multiplying a signal value of one signal of the signal pair input into the input line pair to which the multiplication unit is connected by a positive weight value and a negative weight charge corresponding to a negative weight product value obtained by multiplying a signal value of another signal by a negative weight value
Implementation Method 2
The accumulation unit is capable of accumulating the positive weight charge and the negative weight charge which are generated by each of the plurality of multiplication units
Implementation Method 3
The charging unit charges the accumulation unit in which a charge corresponding to the product value is accumulated after the input period
Implementation Method 4
The output unit performs, after charging by the charging unit starts, threshold determination using a predetermined threshold value on a voltage retained by the accumulation unit, to thereby output a positive multiply-accumulate signal representing a sum of the positive weight product values and a negative multiply-accumulate signal representing a sum of the negative weight product values
Data Source
AI summary
An arithmetic apparatus includes input line pairs and a multiply-accumulate device. A signal pair is input to the input line pairs within an input period. The multiply-accumulate device includes multiplication units, an accumulation unit, a charging unit, and an output unit. The multiplication units generate a positive weight charge and a negative weight charge. The accumulation unit accumulates the positive weight charge and the negative weight charge. The charging unit charges the accumulation unit after the input period. The output unit performs, after charging starts, threshold determination using a predetermined threshold value on a voltage of the accumulation unit, to thereby output a positive multiply-accumulate signal representing a sum of positive weight product values and a negative multiply-accumulate signal representing a sum of negative weight product values.