Analog Neural Chip Coupling for Faster Hybrid ANN Inference

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Solution Overview

Problem

Existing artificial neural networks (ANNs) face inefficiencies in processing speed and data sampling due to sequential node processing in digital ANNs and the need for synchronized operation with less complex networks.

Innovation Solution

Implementing an analogous electrical circuit on a semiconductor chip to form an ANN that processes input data simultaneously across all nodes, coupled recursively with a digital ANN to provide output before the digital network, using the same input data sampling and complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If digital ANNs process nodes sequentially, then device complexity is reduced and ease of operation is improved, but processing speed deteriorates

Engineering Contradiction:
Improveprocessing speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent replaces the sequential digital processing system with an analogous electrical circuit system that processes information through physical electrical signals flowing through circuit elements. This substitution enables simultaneous processing across all nodes through parallel electrical pathways, dramatically increasing processing speed while maintaining manageable complexity through standardized circuit design patterns.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent transitions from one-dimensional sequential processing in digital ANNs to multi-dimensional parallel processing in analogous circuits. By organizing circuit elements in spatial arrays with multiple interconnected pathways, the system processes multiple data points simultaneously across different spatial dimensions, achieving exponential speedup without proportional increases in operational complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If the first ANN provides output before the second ANN, then processing speed is improved, but synchronization complexity increases

Engineering Contradiction:
Improveprocessing speedVSAvoidsynchronization complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by having the first analogous ANN process input data and provide output in advance before the second digital ANN completes its processing. The early output from the first network is stored and ready to influence the second network's processing, enabling time-critical applications where preliminary categorization or filtering accelerates overall system response without requiring complex real-time synchronization.

Inventive Principle:
Principle #10Preliminary action

3Speed

If analogous circuits are used for faster processing, then processing speed is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveprocessing speedVSAvoidmanufacturing precision
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent employs parameter changes by utilizing electrical properties (resistance, capacitance, inductance) of circuit elements that can be precisely controlled during manufacturing. By adjusting these electrical parameters rather than relying solely on geometric precision, the system achieves the required performance characteristics with more relaxed dimensional tolerances. Standard semiconductor fabrication processes can precisely control electrical parameters through material composition and layer thickness rather than requiring ultra-precise feature geometries.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250363343A1System comprising a semiconductor chip, and method for manufacturing the system
Publication Date: 2025.11.27 FRAUNHOFER GESELLSCHAFT ZUR FORDERUNG DER ANGEWANDTEN FORSCHUNG EV
  • US20250363343A1 patent drawing
  • US20250363343A1 patent drawing
  • US20250363343A1 patent drawing

AI summary

The invention relates to a system (110) comprising an input projection layer (111), at least one second digital artificial neural network (50), and at least one semiconductor chip (40) having an analogous artificial neural network (10) being mapped from a trained first digital artificial network (17) wherein the analogous electrical circuit comprises at least one input (20) being configured to receive at least one input signal and at least one output (26) being configured to provide at least one analogous output signal, wherein the analogous artificial neural network (10) electrically connects the input (20) to the output (26), wherein the semiconductor chip (40) is recursively coupled to the second digital artificial neural network (50) such that the output of the semiconductor chip (40) is provided to at least one hidden layer of the second digital artificial neural network (50) and wherein the input (20) of the semiconductor chip (40) and an input layer of the second digital artificial network (50) are electrically connected to the input projection layer (111). The invention provides a fast processing artificial neural network (10) that operates faster than the second digital artificial neural network. Thus, the analogous artificial neural network provides output to influence the operation of the second digital artificial neural network before the second digital artificial neural network provides output.