Current-Mode Analog Neural FFT Circuits Without External ADCs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing neural networks, particularly those used in IoT and edge devices, require analog-to-digital converters (ADCs) to function, which complicates their operation and introduces challenges in managing weighted addition and connectivity between layers, especially in performing complex operations like Fast Fourier Transform (FFT) without significant delay or signal corruption.
Innovation Solution
Analog circuits are designed using transistors to perform frequency decomposition and complex number rotations, utilizing current-mode signaling to encode signals, which allows for efficient computation of FFT without significant current attenuation or delay, enabling stacked neural network layers with low voltage headroom and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If digital neural networks use external ADCs for data conversion, then the network can process analog signals, but the device complexity increases and power consumption rises
Solution Approach 1:
The patent merges the ADC functionality directly into the neural network layer structure by using current-mode signaling throughout. Instead of having separate external ADCs, the analog current signals flow directly through the neural network computations, combining signal conversion and processing into a unified analog computational layer that eliminates external conversion components.
Solution Approach 2:
The current-mode signaling approach provides multi-functionality where the same current signals serve multiple purposes: they represent data values, carry weight information, and enable computational operations simultaneously. This universal current representation eliminates the need for separate digital conversion stages while maintaining full neural network functionality.
2Use of energy by moving object
If analog circuits perform FFT computation using current-mode signaling, then power consumption is reduced and signal distortion is minimized, but the circuit design complexity increases
Solution Approach 1:
The patent replaces traditional voltage-mode electronic circuitry with a current-mode signaling system. This substitution fundamentally changes the domain of operation from voltage to current, enabling direct analog computation of FFT operations without requiring complex voltage conversion stages, thereby reducing overall circuit complexity while maintaining low power consumption.
3Use of energy by moving object
If stacked neural network layers use low voltage headroom, then power consumption decreases, but signal accuracy and computation precision deteriorate
Solution Approach 1:
The patent changes the fundamental operating parameter from voltage to current. By using current-mode signaling throughout the neural network layers, the system achieves accurate computation at low voltage headroom because current signals are less susceptible to voltage noise and can maintain precision even when the voltage supply is minimal, thus resolving the trade-off between power consumption and accuracy.
Data Source
AI summary
An analog circuit configured to receive a current signal for frequency decomposition, the first analog circuit comprising a first transistor including a first source configured to receive a first current, a first drain coupled to a third drain at a third transistor, and a signal input applied to a first gate, a voltage at the first gate determining how much current flows through the first transistor, a second transistor including a second source configured to receive the first current, a second drain coupled to a fourth drain at fourth transistor, and the signal input applied to a second gate, the voltage at the second gate determining how much current flows through the second transistor, the third transistor including a third source configured to receive a second current and the signal input applied to a third gate, the voltage at the third gate determining how much current flows through the third transistor, and the fourth transistor including a fourth source configured to receive the second current and the signal input applied to a first gate, the voltage at the first gate determining how much current flows through the fourth transistor.