Analog Neural Layer Circuits for Reconfigurable Edge AI Hardware
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Solution Overview
Problem
Conventional hardware for neural networks faces challenges in keeping pace with the complexity of neural networks, requiring re-manufacturing after retraining, leading to high costs and inefficiencies, especially in edge applications where low power consumption is essential.
Innovation Solution
Implementing neural networks using a combination of resistors and amplifiers, where resistors with variable resistance adjust to different weights, allowing reuse of hardware for different layers without full re-manufacturing, and utilizing a controller to sequentially implement each layer with selected resistors and amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the entire hardware realization is re-manufactured after neural network retraining, then the neural network can be retrained for new tasks, but hardware costs increase significantly and manufacturing time is extended
Solution Approach 1:
The hardware realization is divided into multiple neural layer circuits, each corresponding to a specific layer of the neural network. Only the resistors in the relevant neural layer circuit need to be reconfigured when retraining occurs, rather than re-manufacturing the entire chip. This segmentation allows partial reconfiguration of specific layers while maintaining the rest of the hardware structure.
Solution Approach 2:
Each neural layer circuit is designed to be multi-functional, capable of implementing different neural network layers by reconfiguring the resistor values. The same physical hardware structure can serve multiple purposes by adjusting the resistance values of selected resistors, allowing a single chip to support neural network retraining without full re-manufacturing.
2Productivity
If more neural network layers are implemented on the same substrate, then the computational capability increases, but the chip area and complexity increase
Solution Approach 1:
Neural layer circuits are designed to be reusable across multiple layers. By configuring different sets of resistors within the same physical circuit structure, a single neural layer circuit can implement multiple different neural network layers through reconfiguration, reducing the total chip area required.
Solution Approach 2:
The resistor values in the neural layer circuits are made variable and reconfigurable. This dynamic property allows the same hardware structure to adapt to different layer requirements by changing resistance values, enabling multiple layers to share the same physical substrate without requiring dedicated fixed hardware for each layer.
3Adaptability or versatility
If variable resistance mechanisms are added to resistors to enable reconfiguration, then neural network retraining becomes possible, but device complexity increases
Solution Approach 1:
The invention changes the resistance parameter of selected resistors to enable retraining. By using variable resistors or resistors with adjustable resistance values, the hardware can be reconfigured for different neural network layers without requiring complete hardware replacement, achieving reprogrammability through parameter modification rather than structural changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces hardware costs and time-to-market by allowing efficient reprogramming and reuse of neural network layers, providing improved performance per watt and enabling low-power edge applications.
Implementation Method 1
In some embodiments, the at least one resistor has variable resistance that is adjusted based on one of a plurality of mechanisms
Data Source
AI summary
Systems, devices, integrated circuits, and methods are provided for layer-based analog hardware realization of neural networks. An electronic device includes a collection of resistors, a collection of amplifiers, and a controller. The controller is configured to implement each of the plurality of layers sequentially. For each of the plurality of layers, the controller extracts, from memory, a plurality of layer parameters corresponding to a plurality of weights of the respective layer, and in accordance with the plurality of layer parameters, selects a plurality of resistors and a plurality of amplifiers and forms a set of input resistors from the plurality of resistors. The set of input resistors are electrically coupled to the plurality of amplifiers to form a neural layer circuit. The neural layer circuit may obtain a plurality of input signals via the plurality of resistors and generate a plurality of output signals from the plurality of input signals.