Analog Neural Memory Array Programming Mechanism
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Solution Overview
Problem
Existing artificial neural networks face challenges in achieving high performance information processing due to inadequate hardware technology, specifically in terms of high cost and mediocre energy efficiency, as well as the bulkiness of CMOS-implemented synapses.
Innovation Solution
The development of analog neural memory arrays using non-volatile memory cells, where two or more memory cells are grouped to form a logical cell that can be programmed using different mechanisms, such as coarse, fine, and ultra-fine programming, to achieve extreme programming accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital supercomputers or specialized graphics processing unit clusters are used to achieve high connectivity and computational parallelism, then the computational capability is improved, but the cost increases and energy efficiency deteriorates
Solution Approach 1:
The patent replaces digital computational systems (supercomputers, GPU clusters) with an analog neuromorphic memory system that performs computation through physical electrical phenomena. Memory cells conduct current proportional to their stored weight values, enabling direct analog multiplication of inputs by weights without digital processing, thereby improving energy efficiency while maintaining computational capability
Solution Approach 2:
The patent makes neuromorphic memory serve dual functions: it acts as both storage memory for neural network weights and as the computational engine for performing multiply-accumulate operations. This eliminates the need for separate processing units, reducing overall system complexity and energy consumption while maintaining high computational parallelism
2Use of energy by moving object
If CMOS analog circuits are used to implement synapses, then the energy efficiency is improved, but the area occupied by each synapse increases
Solution Approach 1:
The patent replaces bulky CMOS analog circuit implementations with compact non-volatile memory cell structures (such as flash memory cells with floating gates). These memory cells naturally exhibit analog conductance properties that can be programmed to represent weights, eliminating the need for complex CMOS analog circuits while reducing area and improving energy efficiency
Solution Approach 2:
The patent utilizes composite memory cell structures combining multiple functional elements (floating gate, control gate, channel region, insulating layers) within a single compact unit. This composite structure integrates storage and computation functions in one element, achieving high energy efficiency without the area overhead of separate CMOS analog circuit components
3Measurement precision
If multiple programming mechanisms are used within a logical cell, then the programming accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent divides the programming process into distinct segmented stages: coarse programming for initial weight assignment, fine programming for precision adjustment, and ultra-fine programming for final calibration. Each stage uses appropriately sized voltage pulses tailored to the required precision level, achieving high overall accuracy without requiring a single complex programming mechanism
Solution Approach 2:
The patent applies progressively smaller voltage pulses in subsequent programming stages rather than using one large complex mechanism. Coarse programming uses larger pulses for rapid initial programming, fine programming uses medium pulses for precision adjustment, and ultra-fine programming uses small pulses for final calibration. This partial action approach achieves extreme accuracy through cumulative refinement rather than a single excessive action
Data Source
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AI summary
Numerous embodiments of analog neural memory arrays are disclosed. Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.