Analog Neural Memory Cell Verification Circuit
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Solution Overview
Problem
Existing artificial neural networks face challenges in programming and verifying non-volatile memory cells with the precision required for high-performance vector-by-matrix multiplication, particularly in storing and retrieving specific weight values for analog neuromorphic memory systems.
Innovation Solution
The development of systems and methods that allow for precise programming, verification, and reading of non-volatile memory cells in analog neuromorphic memory systems, enabling continuous and independent change of memory states to store multiple discrete values, such as 16 or 64 different values, for precise tuning of synapse weights in neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If non-volatile memory cells are programmed to store multiple discrete values (16 or 64 different values), then the precision of synapse weight representation is improved, but the complexity of programming and verification increases
Solution Approach 1:
The patent implements a verify operation that reads the programmed value from the memory cell and compares it against the target value. If the programmed value does not match the target value, the programming process is repeated with adjusted parameters. This feedback mechanism enables precise control of synapse weights (achieving 16 or 64 discrete levels) while managing programming complexity through iterative correction rather than requiring perfect single-pass programming.
2Use of energy by moving object
If analog neuromorphic memory is used to achieve high computational parallelism, then the energy efficiency is improved, but the difficulty of programming selected cells with precision increases
Solution Approach 1:
The patent segments the memory array into individually addressable memory cells with separate word lines and bit lines. This segmentation allows selected cell programming by activating specific word lines and bit lines simultaneously, isolating the target cell from others. The segmentation enables precise programming of individual cells within the analog memory array while maintaining the energy-efficient parallel architecture, as each cell can be programmed independently without affecting others.
3Productivity
If a large number of memory cells are used to achieve high connectivity between neurons, then the computational parallelism is improved, but the area required for the memory array increases
Solution Approach 1:
The patent merges the storage function and computation function into a single memory array structure. The memory cells simultaneously serve as weight storage elements and as the computational engine for vector-matrix multiplication. By applying voltages to word lines and bit lines, the system performs parallel multiplication and summation operations directly in the memory array, eliminating the need for separate compute units. This merging enables high computational parallelism while minimizing the area required, as the same physical structure serves multiple functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables precise programming and verification of memory cells, enhancing the ability to store and adjust synapse weights in neural networks with high precision, improving the energy efficiency and computational parallelism of artificial neural networks.
Implementation Method 1
Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate
Implementation Method 2
The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs
Data Source
AI summary
In one example, a circuit for comparing current drawn by a selected memory cell for a vector-matrix-multiplier with current drawn by a reference matrix comprises a first circuit comprising a first PMOS transistor coupled to a first NMOS transistor coupled to the selected memory cell; and a second circuit comprising a second PMOS transistor coupled to a second NMOS transistor coupled to the reference matrix; wherein a node between the second PMOS transistor and the second NMOS transistor outputs a current indicative of a value stored in the selected memory cell.