Analog Neuromorphic Circuits With Resistive-Memory Parallel Multiply-Add
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Solution Overview
Problem
Conventional microprocessor technology is limited by chronological operation execution, leading to inefficiencies in computational performance, power consumption, and physical size, making it unsuitable for applications requiring significant computational efficiency like image recognition, and neuromorphic computing networks are too large and power-hungry for industries such as biomedical, military, and mobile devices.
Innovation Solution
Analog neuromorphic circuits utilizing resistive memories are designed with a crossbar configuration, allowing parallel execution of multiplication and addition operations, leveraging nano-scale memristors for low power consumption and high computational efficiency, enabling compact neuromorphic systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional microprocessor technology is used, then operations are completed in chronological order, but computational efficiency and performance are limited
Solution Approach 1:
The computing system is segmented into multiple independent processing units (neurons) that can operate simultaneously. Each neuron processes operations in parallel rather than sequentially, dividing the computational workload into concurrent tasks that execute independently, thereby resolving the chronological execution limitation of conventional microprocessors.
Solution Approach 2:
The system transitions from one-dimensional sequential processing to multi-dimensional parallel processing. By implementing spatial architecture where multiple neurons are arranged in parallel, the system executes operations across multiple dimensions simultaneously, enabling exponential increase in computational efficiency without proportionally increasing time loss.
2Productivity
If conventional neuromorphic computing networks are implemented, then computational efficiency increases, but physical size and power consumption increase significantly
Solution Approach 1:
The patent replaces conventional mechanical/electronic computing architectures with a neuromorphic system that uses biological-inspired principles. By substituting traditional processor-based computation with membrane potential-based neural networks, the system achieves high computational efficiency while reducing physical footprint and power consumption through distributed parallel processing.
Solution Approach 2:
Each neuron in the network performs multiple functions simultaneously - processing inputs, applying weights, generating outputs, and participating in parallel computations. This multi-functionality allows the system to achieve high computational efficiency without requiring separate dedicated components for each function, thereby reducing overall physical size.
3Productivity
If conventional neuromorphic computing networks are implemented, then computational efficiency increases, but power consumption increases significantly
Solution Approach 1:
The neural network operates through periodic action potentials and membrane potential changes rather than continuous high-power processing. By using event-driven computation where neurons fire only when necessary to process inputs, the system maintains high computational efficiency while significantly reducing average power consumption compared to conventional continuous-processing architectures.
Solution Approach 2:
The neuromorphic system performs self-regulation through membrane potential dynamics and threshold-based firing mechanisms. Each neuron automatically adjusts its state based on incoming signals without requiring external control, enabling efficient energy usage where computation occurs only when needed, thereby reducing overall power consumption while maintaining high productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves exponentially higher computational efficiency with significantly reduced power and size, enabling applications like image recognition and learning algorithms in compact form factors suitable for mobile and resource-constrained environments.
Implementation Method 1
The plurality of resistive memories is configured to provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current
Implementation Method 2
each corresponding current is added in parallel
Data Source
AI summary
An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.


