Analog Neuron with S-Domain Memory for AI Networks
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Solution Overview
Problem
Existing artificial intelligence (AI) networks struggle to implement memory of previous states in an analog computer system, as digital clocking intervals are not applicable, and analog circuits require a continuous time system for higher speed and lower power consumption.
Innovation Solution
A continuous time analog element is developed for use as a neuron in AI networks, utilizing resistors, buffers, all-pass filters, and finite gain integrators to provide memory of prior layer states without discrete clocking intervals, replacing digital z-domain operations with analog s-domain operators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If digital AI networks use discrete clocking intervals, then memory of previous states can be implemented, but speed and power consumption are limited
Solution Approach 1:
The patent replaces the digital mechanical clocking system with an analog continuous-time system. The discrete clocking mechanism is substituted by continuous analog signals that operate without periodic interruption, enabling higher processing speeds and lower power consumption while maintaining memory functionality through analog feedback loops.
Solution Approach 2:
The patent changes the fundamental parameter of time representation from discrete (digital clocking intervals) to continuous (analog time). This parameter change allows the system to operate continuously without discrete timing constraints, achieving improved speed and energy efficiency while maintaining the ability to remember previous states through continuous feedback.
2Productivity
If analog AI networks operate in continuous time, then higher speed and lower power consumption are achieved, but memory of previous states becomes difficult to implement
Solution Approach 1:
The patent introduces feedback mechanisms in the form of continuous-time feedback loops that connect neural units to their own previous states. This feedback structure enables the analog system to remember previous states reliably while maintaining continuous-time operation, thus achieving both high processing efficiency and reliable memory functionality simultaneously.
Solution Approach 2:
The patent designs analog neural units that perform multiple functions: they process current inputs, remember previous states, and provide feedback all within a single continuous-time circuit. This multi-functionality eliminates the need for separate discrete memory components, achieving reliable memory functionality while maintaining the productivity benefits of continuous-time operation.
3Loss of time
If digital z-domain operations are used, then discrete time memory is achieved, but system complexity increases
Solution Approach 1:
The patent substitutes complex digital z-domain operations with simpler analog s-domain operations. The discrete time handling complexity is replaced by continuous-time analog circuitry, which inherently handles time without requiring discrete clocking mechanisms, thereby reducing overall system complexity while maintaining effective time management.
Solution Approach 2:
The patent changes the mathematical domain from discrete (z-domain) to continuous (s-domain). This parameter change simplifies the system by eliminating the need for discrete time steps and clocking mechanisms, reducing hardware complexity while achieving effective time handling through continuous analog operations.
Data Source
AI summary
An analog element for use as a neuron in a recurrent neural network is described, the analog element having memory of a prior layer state and being a continuous time circuit rather than having a discrete clocking interval. The element is characterized and described by the Laplace s-domain operator, as distinct from a digital solution that uses the z-domain operator appropriate for quantized time descriptions. Rather than using an all-pass filter, the analog equivalent of a unit delay in the z-domain, a finite gain integrator, which is a simpler circuit, may be used to provide the delay in the analog s-domain. The resulting circuit may be easily implemented at the transistor level.