Analog PLL Dual Phase Detector Fast Acquisition
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Solution Overview
Problem
Analog phase-locked loops (PLLs) face slow acquisition during start-up and frequency switching due to the inability to detect large phase errors, as existing phase detectors can only handle phase errors within 2π radians, limiting the efficiency of the charge pump and oscillator frequency adjustment.
Innovation Solution
Incorporating a further phase detector capable of detecting phase errors as integer multiples of 2π, which controls a second charge pump to provide currents proportional to the detected phase error, allowing for faster acquisition by enabling a larger charge pump current without increasing circuit complexity or area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional phase detector is used, then the circuit complexity is low, but the acquisition time is slow because large phase errors cannot be detected
Solution Approach 1:
The phase detection function is segmented into two independent detectors: a first phase detector for detecting phase errors within one cycle (2π radians) and a second phase detector for detecting integer multiples of 2π. This segmentation allows each detector to specialize in a specific range, enabling fast acquisition of large phase errors while maintaining simple circuit implementation for each individual detector.
Solution Approach 2:
The dual phase detector system provides multi-functionality by handling both small phase errors (within 2π) and large phase errors (multiples of 2π) within the same PLL circuit. The first phase detector maintains high resolution for fine tuning, while the second phase detector enables rapid acquisition of large frequency offsets, making the system universally applicable to both acquisition and tracking phases.
2Loss of time
If the charge pump current is increased to speed up acquisition, then the acquisition time decreases, but the loop stability deteriorates
Solution Approach 1:
The system dynamically switches between two charge pump configurations based on the acquisition phase. During initial acquisition with large frequency offsets, the second charge pump operates with higher current to rapidly reduce the phase error. Once the phase error is within the detectable range of the first phase detector, the system transitions to using the first charge pump with lower current to maintain loop stability during tracking. This dynamic adaptation allows fast acquisition without compromising stability.
Solution Approach 2:
The second phase detector acts as an intermediary that bridges the gap between large frequency offsets and the limited range of the first phase detector. By detecting integer multiples of 2π, it provides intermediate information that enables the charge pump to make larger adjustments without directly overloading the main phase detector, thus facilitating faster acquisition while preserving loop stability through controlled current distribution.
3Adaptability or versatility
If frequency dividing is used to extend phase detector range, then large phase errors can be detected, but the device complexity increases due to additional dividers
Solution Approach 1:
Instead of modifying the main phase detector with frequency dividers, the invention creates a copy function through the second phase detector that specifically counts integer multiples of 2π. This copying approach allows the system to handle large phase errors without altering the original high-resolution phase detector, maintaining its simple structure while extending the overall detection capability through the parallel second detector.
Data Source
AI summary
An analog phase-locked loop (PLL) is disclosed, comprising a voltage controlled oscillator (VCO); a frequency divider having its input connected to an output of the VCO; a first phase detector arranged to detect a phase difference between an output signal of the frequency divider and a reference frequency signal and provide an output signal based on the phase difference, wherein the detectable phase difference is within one cycle of the reference frequency; a first charge pump connected to an output of the first phase detector and arranged to output a charge per detected phase error based on the output of the first phase detector; and an analog loop filter connected to the first charge pump and arranged to provide a voltage, based on the output of the first charge pump, to the VCO. The PLL further comprises a second phase detector arranged to detect a number of cycles in phase difference between the output signal of the frequency divider and the reference frequency signal and provide an output signal based on the number of cycles in phase difference; and a second charge pump connected to an output of the second phase detector and arranged to provide a charge per detected phase error, based on the output of the second phase detector, to the loop filter. A radio circuit, a communication device and a communication node are also disclosed.