Analog PLL Dual Phase Detection for Faster Acquisition
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Solution Overview
Problem
Analog phase-locked loops (PLLs) face slow acquisition during start-up and frequency switching due to the inability of traditional phase detectors to handle phase errors larger than 2π radians, limiting the efficiency of the charge pump and loop voltage control.
Innovation Solution
Incorporating a further phase detector capable of detecting phase errors as integer multiples of 2π, which controls a second charge pump to provide currents proportional to the detected phase error, allowing for faster acquisition and improved settling speed without increasing circuit complexity or area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a traditional phase detector is used, then the circuit complexity is low, but the acquisition speed is slow because it cannot detect phase errors larger than 2π radians
Solution Approach 1:
The phase detection function is segmented into two independent detectors: a first phase detector for detecting phase errors within one cycle (2π radians) and a second phase detector for detecting integer multiples of 2π radians. This segmentation allows each detector to specialize in a specific range, enabling fast acquisition through the second detector while maintaining simple circuitry through the first detector.
Solution Approach 2:
The invention extends the phase error detection capability from a single-dimensional range (0 to 2π) to a multi-dimensional range by adding the second phase detector that operates in integer multiples of 2π radians. This dimensional extension allows the system to handle large phase errors during acquisition without increasing the complexity of individual detector circuits.
2Productivity
If the charge pump current is increased to speed up acquisition, then the settling speed improves, but the loop becomes unstable requiring additional circuitry
Solution Approach 1:
The system dynamically switches between two charge pumps based on the acquisition state. During acquisition, the second charge pump provides large current for fast settling. Once locked, the system transitions to using the first charge pump for stable, precise frequency control. This dynamic operation allows the system to achieve both fast settling and stability without requiring complex stability compensation circuitry.
3Measurement precision
If a single high-precision charge pump is used, then the phase accuracy is maintained, but the acquisition speed is limited by the charge pump's current capability
Solution Approach 1:
The charge pump function is segmented into two parallel paths: the first charge pump maintains high precision for phase-locked operation, while the second charge pump provides high current for fast acquisition. This segmentation resolves the contradiction by allowing each charge pump to optimize for its specific function without compromising the other.
Solution Approach 2:
The dual charge pump system provides multi-functionality: during acquisition, the second charge pump dominates to provide fast frequency pulling; during phase-locked operation, the first charge pump maintains precision. The system universally handles both acquisition and tracking requirements through two specialized charge pumps working in different operational modes.
Data Source
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AI summary
An analog phase-locked loop, PLL, (100, 200) is disclosed, comprising a voltage controlled oscillator (102, 202); a frequency divider (104, 204) having its input connected to an output of the VCO; a first phase detector (106, 206) arranged to detect a phase difference between an output signal of the frequency divider and a reference frequency signal and provide an output signal based on the phase difference, wherein the detectable phase difference is within one cycle of the reference frequency; a first charge pump (108, 208) connected to an output of the first phase detector and arranged to output a charge per detected phase error based on the output of the first phase detector; and an analog loop filter (110, 210) connected to the first charge pump and arranged to provide a voltage, based on the output of the first charge pump, to the VCO. The PLL further comprises a second phase detector (112, 212, 300, 400, 500) arranged to detect a number of cycles in phase difference between the output signal of the frequency divider and the reference frequency signal and provide an output signal based on the number of cycles in phase difference; and a second charge pump (114, 214, 600, 700) connected to an output of the second phase detector and arranged to provide a charge per detected phase error, based on the output of the second phase detector, to the loop filter. A radio circuit, a communication device and a communication node are also disclosed.