Analog PLL Lock Detection With Delay-Based Ripple Suppression
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Solution Overview
Problem
Phase lock loops (PLLs) require a simple and effective lock detection mechanism that eliminates the complexity of digital lock detectors while maintaining a stable lock indication signal without ripple.
Innovation Solution
An analog lock detector comprising a detector, logic gate, delay circuit, and guard gate inverter, which outputs a final lock signal with a steady state indicating frequency lock without brief intervals of deviation, using a combination of up and down signals and time delays to stabilize the lock indication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a digital lock detector is used to detect PLL lock status, then the lock indication signal can be generated, but the device complexity increases due to higher transistor count and digital circuit requirements
Solution Approach 1:
The patent replaces the digital lock detector with an analog lock detector that uses continuous voltage signals instead of discrete digital logic. The analog detector compares the VCO output frequency with the reference frequency using analog circuitry (including a delay circuit and comparator), eliminating the need for complex digital transistor-based logic gates and registers, thereby reducing device complexity while maintaining reliable lock detection
Solution Approach 2:
The patent changes the detection parameter from digital logic levels to analog voltage levels. By monitoring the continuous voltage relationship between the VCO output and reference frequency signals, the system achieves accurate lock detection through analog parameter comparison rather than digital state evaluation, reducing the transistor count required
2Device complexity
If a simple lock detector is used to reduce device complexity, then the transistor count decreases, but the lock indication signal may contain ripple during locked intervals
Solution Approach 1:
The patent introduces a delay circuit as an intermediary element between the frequency comparison stage and the lock indication output. This delay circuit holds the lock status signal for a predetermined time period, allowing brief ripple or transient deviations to settle before the final lock indication is generated, thereby stabilizing the output signal while maintaining simple analog circuitry
Solution Approach 2:
The patent applies beforehand cushioning by incorporating a predetermined delay period that anticipates and absorbs potential signal ripple or transient instability. This delay acts as a buffer that smooths out brief deviations from the steady state before they reach the final lock indication output, ensuring stable signal composition without requiring complex stabilization circuits
3Ease of manufacture
If the lock detection circuit is simplified, then ease of manufacture improves, but the ability to filter brief intervals of deviation from steady state deteriorates
Solution Approach 1:
The patent replaces complex digital filtering circuits with a simple analog delay mechanism. The delay circuit, implemented using basic analog components (such as a capacitor-resistor network or simple latch circuit), provides the necessary filtering of brief deviation intervals while being easy to manufacture and integrate into the PLL circuitry, maintaining ease of manufacture while ensuring reliable ripple elimination
Data Source
AI summary
An analog lock detector for a phase lock loop includes a detector, a logic gate, a delay circuit, and a guard gate inverter. The detector outputs up and down signals relating synthesized and reference frequencies. The logic gate outputs an initial lock signal combining the up and down signals. While the synthesized and reference frequencies are locked, the initial lock signal has a steady state except during brief intervals. The delay circuit outputs a delayed lock signal that time delays the initial lock signal by a delay amount, which matches a maximum allowed duration of the brief intervals while locked. A guard gate inverter outputs a final lock signal that combines the initial lock signal and the delayed lock signal. The final lock signal has the steady state indicating when the synthesized frequency is locked to the reference frequency, but without the brief intervals of deviation from the steady state.