Analog PLL Tracking Loop for Stable Phase Difference

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Solution Overview

Problem

Analog phase locked loops (PLLs) face challenges in maintaining frequency stability due to variable phase errors, which are not suitable for applications requiring constant phase difference between reference and feedback signals, limiting the use of Type I PLLs despite their advantages in locking time and phase noise vs power trade-off.

Innovation Solution

The proposed analog PLL incorporates a tracking loop with a comparator, integrator, and proportional integral derivative controllers to adjust the tuning and tracking voltages, allowing for quasi-type-II operation and reducing phase errors, while a summing element combines these voltages to control the VCO, ensuring stable frequency output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If Type I PLL is used, then locking time and phase noise vs power trade-off are improved, but phase difference between reference and feedback signals becomes variable which is not suitable for applications requiring constant phase difference

Engineering Contradiction:
Improvelocking timeVSAvoidphase difference stability
Core Design Contradiction:
Loss of timeVSStability of the object's composition

Solution Approach 1:

The control signal generation is segmented into two independent paths: a phase detector path that generates phase error signal for frequency locking, and a tracking loop path that generates tracking voltage for phase difference control. This segmentation allows Type I PLL to achieve constant phase difference while maintaining fast locking characteristics.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A tracking loop is introduced as an intermediary mechanism between the phase detector and VCO. The tracking loop receives the phase detector signal, compares it with a target voltage, and generates a tracking voltage that controls the VCO to maintain constant phase difference, while the phase detector independently handles frequency locking.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Stability of the object's composition

If Type II PLL operation is implemented to maintain constant phase difference, then phase stability is improved, but device complexity increases due to additional tracking loop components

Engineering Contradiction:
Improvephase difference stabilityVSAvoidtracking loop complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The tracking loop is merged with the existing phase detector and low-pass filter components. The phase detector signal serves dual purposes: controlling frequency through the low-pass filter and controlling phase difference through the tracking loop. This merging reduces overall system complexity while achieving Type II PLL functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The phase detector signal is made multi-functional, serving both as the input to the traditional low-pass filter for frequency control and as the input to the tracking loop for phase difference control. This universality eliminates redundant components and simplifies the overall architecture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If tracking loop with integrator is used, then frequency stability is improved, but device complexity and power consumption increase

Engineering Contradiction:
Improvefrequency stabilityVSAvoidcontroller complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The integrator function is extracted from the main control path and placed specifically within the tracking loop. This allows the integrator to operate only on the tracking voltage signal, reducing its impact on overall system complexity and power consumption while still providing the necessary frequency stability through cumulative error correction.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11489532B2Analog phase locked loop
Publication Date: 2022.11.01 NXP BV
  • US11489532B2 patent drawing
  • US11489532B2 patent drawing
  • US11489532B2 patent drawing

AI summary

An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.