Analog PLL Ramp-Slope Locking for Low-Power High-Frequency Control
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Solution Overview
Problem
Conventional digital phase lock loop (PLL) circuits consume high power and occupy large area due to the use of bipolar transistors and digital dividers, limiting their frequency operation and footprint on integrated circuits.
Innovation Solution
An all-analog PLL system utilizing operational amplifiers (op-amps) and CMOS field effect transistors to integrate reference and VCO frequencies into ramp slopes, comparing these slopes to lock the VCO frequency to the reference frequency without digital components, thereby reducing power consumption and increasing operational frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If digital circuits with bipolar transistors are used in conventional PLL, then frequency locking capability is achieved, but power consumption increases and circuit area increases
Solution Approach 1:
The patent replaces digital electronic circuits with bipolar transistors with an analog mechanical-style system using op-amps and integrators that generate and compare ramp slopes. This substitution eliminates the need for complex digital logic while achieving the same frequency locking function through continuous analog signal processing, thereby reducing power consumption and circuit area.
Solution Approach 2:
The patent changes the operating parameters from digital discrete levels to analog continuous ramp slopes. By integrating clock signals to produce ramp waveforms and comparing their slopes, the system operates in a different parameter domain that requires simpler, lower-power circuitry while maintaining frequency locking capability.
2Productivity
If digital dividers are used in conventional PLL, then frequency division is achieved, but circuit footprint area increases
Solution Approach 1:
The patent replaces digital divider circuits with an analog integration and comparison system. Instead of using complex digital logic to divide frequencies, the system integrates both reference and VCO clock signals and compares the resulting ramp slopes, achieving frequency division functionality through simpler analog components that occupy less area.
Solution Approach 2:
The integrator circuits serve multiple functions simultaneously: they act as frequency dividers, phase detectors, and slope generators all in one component. This multi-functionality eliminates the need for separate digital divider circuits, reducing the overall circuit footprint while maintaining frequency division capability.
3Reliability
If digital circuits are used in conventional PLL, then frequency locking is achieved, but operational frequency is limited
Solution Approach 1:
The patent replaces digital circuits with analog op-amp based integrators and comparators that have inherently faster response times. The continuous analog signal processing eliminates digital switching delays and allows the PLL to operate at higher frequencies while maintaining stable frequency locking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The all-analog PLL system achieves frequency lock more quickly and occupies less area on integrated circuits compared to digital PLL systems, allowing higher frequency operation with reduced power consumption.
Implementation Method 1
a first integrator to integrate the reference frequency into a first ramp slope
Implementation Method 2
a second integrator to integrate the VCO frequency into a second ramp slope
Implementation Method 3
a slope comparator to generate a slope difference between the first ramp slope and the second ramp slope
Implementation Method 4
a third integrator to integrate the VCO frequency into successive ramp slopes
Implementation Method 5
a comparator to compare the successive ramp slopes against a direct current (DC) threshold voltage, to produce a regenerated frequency
Data Source
AI summary
A phase locked loop (PLL) comprises: a reference oscillator to generate a reference clock having a reference frequency; a voltage controlled oscillator (VCO) to generate a VCO clock having a VCO frequency controlled in response to a control signal applied to the VCO; a first integrator to integrate the reference frequency into a first ramp slope; a second integrator to integrate the VCO frequency into a second ramp slope; and a slope comparator to generate a slope difference between the first ramp slope and the second ramp slope and that is conveyed by the control signal, such that the control signal is configured to drive the VCO frequency toward the reference frequency to minimize the slope difference and frequency lock the VCO frequency to the reference frequency.