Programmable Analog Processing Array for Reconfigurable Time-Discrete Signals
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Solution Overview
Problem
Existing programmable analog signal processing arrays lack flexibility and efficiency in processing analog signals due to fixed hardware configurations and limited programmability, which restricts their ability to adapt to various signal processing functions and resolutions.
Innovation Solution
A programmable analog signal processing array comprising a network of pre-configurable processing slices with switchable clock input, delay, multiplier, adder, and resample elements, allowing for cell-individual pre-configuration and dynamic re-configuration during operation, enabling time-discrete signal processing and in-memory computing without requiring increased hardware for higher signal resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed hardware configurations are used in analog signal processing arrays, then device complexity is reduced, but adaptability and versatility deteriorate
Solution Approach 1:
The patent implements dynamic reconfigurability by allowing the analog processing array to change its operational characteristics during runtime. The processing elements can be dynamically programmed to perform different signal processing functions (e.g., filtering, convolution, correlation) by modifying the weights and connections between elements, enabling a single fixed hardware structure to adapt to multiple processing tasks without physical reconfiguration
Solution Approach 2:
The patent creates a universal analog processing array where a single fixed hardware architecture can perform multiple signal processing functions. By using a standardized array of processing elements with programmable weights and connections, the system achieves multi-functionality across different applications (FIR filters, IIR filters, rank filters, neural network operations) without requiring separate dedicated hardware for each function
2Measurement precision
If higher signal resolution is achieved through increased hardware, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent achieves higher signal resolution by optimizing analog parameters (voltage levels, current densities, capacitor values, resistor ratios) within the existing hardware architecture rather than increasing hardware quantity. By carefully controlling the precision of analog component values and their ratios, the system attains high-resolution signal processing (e.g., 12-bit or higher effective resolution) without requiring proportionally more hardware elements
Solution Approach 2:
The patent replaces digital sampling and processing mechanisms with continuous-time analog processing to achieve high resolution. By maintaining signals in the analog domain throughout the processing array and only converting to digital at the output, the system preserves signal precision without the quantization losses inherent in repeated digital conversions, effectively substituting analog continuity for digital discretization
3Manufacturing precision
If fixed-function analog processing arrays are used, then manufacturing precision requirements are reduced, but adaptability deteriorates
Solution Approach 1:
The patent implements dynamic programmability that allows the system to compensate for manufacturing variations. By enabling runtime adjustment of weights, thresholds, and connection patterns through digital-to-analog converters and programmable resistive elements, the system can adapt to actual circuit characteristics despite fabrication tolerances, achieving consistent performance across different manufacturing batches without requiring ultra-precise fabrication
Data Source
AI summary
A programmable analog processing array for programmable time-discrete processing of analog input signals in accordance with a desired signal processing function comprises a network of mutually interconnectable and pre-configurable analog processing slices that form unit circuit cells of the network. Each processing slice comprises a set of cell circuit elements including: a switchable clock input port for receiving a clock signal, a delay element for receiving a respective analog slice input signal and for forwarding the received slice input signal with a pre-configurable time delay as a respective delayed slice input signal, an analog multiplier element receiving the delayed slice input signal for providing an analog multiplier output signal corresponding to a product of the delayed slice input signal with a pre-configurable multiplication factor, an analog adder element receiving a pre-configurable selection of at least two adder input signals including the multiplier output signal and for providing an analog adder output signal corresponding to a sum of the adder input signals, and including an analog resample element for receiving the adder output signal and for providing the received adder output with a pre-configurable time delay as an analog slice output signal.