Analog Read Circuit for ST-MRAM Bit Selection
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Solution Overview
Problem
In spin-torque magnetoresistive random access memory (ST-MRAM) technology, increasing variability in magnetic tunnel junction (MTJ) resistance and high switching currents limit scalability, and existing methods for testing and failure analysis require additional selection circuitry that increases chip area and power consumption.
Innovation Solution
A method and apparatus for selectively enabling analog read, digital read, or write operations in a bit cell array using a latch to store data and an analog read circuit that reuses elements of the standard data path, allowing for individual bit selection and reducing the need for additional circuitry, along with a reconfiguration register to selectively access portions of a page, thereby minimizing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional selection circuitry is added to enable individual bit selection for testing and failure analysis, then measurement precision and ease of operation are improved, but device complexity and chip area increase
Solution Approach 1:
The patent makes the existing data path circuitry multi-functional by enabling it to perform both standard memory operations and analog read operations for test and failure analysis. The same bit line, source line, and sense amplifier infrastructure is reused for both data access and resistance measurement, eliminating the need for dedicated test circuitry.
Solution Approach 2:
The memory array's own data path circuitry is utilized to perform self-diagnosis and self-testing functions. The existing infrastructure serves its primary function while also enabling test operations without requiring external or additional specialized equipment.
2Ease of operation
If additional selection circuitry is added to enable individual bit selection, then ease of operation is improved, but power consumption increases
Solution Approach 1:
The data path circuitry is designed to handle both normal memory operations and test operations using the same physical infrastructure. By making the bit lines, source lines, and sense amplifiers multi-functional, the patent avoids the power overhead of maintaining separate dedicated test circuitry.
3Device complexity
If chip area is reduced by removing additional circuitry, then device complexity is reduced, but ease of manufacture and adaptability worsen
Solution Approach 1:
The patent introduces dynamic control mechanisms (control signals, timing sequences) that enable the static data path circuitry to perform different functions. Through dynamic activation and configuration, the same hardware infrastructure adapts between normal operation mode and test mode, providing versatility without additional physical circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient selective operation on individual bits within the ST-MRAM array, reducing chip area and power consumption by reusing existing circuitry and allowing for precise control over bit operations during testing and failure analysis, while maintaining high-density data storage capabilities.
Implementation Method 1
exhibits an electrical resistance that depends on the magnetic state of the device
Implementation Method 2
The angular momentum carried by the spin-polarized tunneling current causes reversal of the free layer
Data Source
AI summary
An analog read circuit measures the resistance of each of a plurality of bits in an array of resistive memory elements. Data stored within a latch determines whether to selectively enable the analog read circuit. In an alternate embodiment, a sense amplifier is coupled to the latch and the array, and the data stored in the latch determines whether to selectively enable the sense amplifier.