Analog Sampling Circuit With Overlap Switching for Clock Slew Robustness
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Solution Overview
Problem
Conventional charge-based sampling circuits for high-speed analog-to-digital converters are sensitive to clock slew rate, leading to sampling errors and require complex clock mechanisms, which increase power consumption and design complexity, especially in time-interleaved systems.
Innovation Solution
A charge-based sampling circuit with a four-phase operation that includes an overlap phase, where the reset and sampling switches have equal duty factors and a phase delay, reducing sensitivity to clock slew rate and simplifying control signal generation, thereby reducing power consumption and design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If charge-based sampling circuits are used for high-speed operation, then bandwidth and jitter performance are improved, but power consumption and control mechanism complexity increase
Solution Approach 1:
The sampling circuit operation is segmented into four distinct phases (reset, overlap, integration, hold) with equal duty factors, allowing each phase to be optimized independently while maintaining overall high-speed performance with reduced power consumption
2Speed
If time-interleaved charge-based sampling circuits are used to increase sampling rate, then bandwidth is improved, but clock mechanism complexity and power consumption increase dramatically
Solution Approach 1:
The circuit uses parameter changes in the control signals (equal duty factors, specific phase delays less than the duty factor) to achieve high-speed time-interleaved operation without requiring complex clock generation and distribution mechanisms
3Speed
If conventional high-speed sampling circuits are used, then sampling speed is improved, but sensitivity to clock slew rate increases causing sampling errors
Solution Approach 1:
The circuit introduces an asymmetric overlap phase where the reset switch remains closed while the sampling switch closes, creating a controlled asymmetric transition that reduces sensitivity to clock slew rate variations and eliminates input-dependent sampling time variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly reduces the sampling circuit's sensitivity to clock slew rate, simplifies control signal generation, and achieves high sampling bandwidth with reduced power consumption, making it suitable for wideband data communication systems.
Implementation Method 1
a capacitive means, a reset switch, and a sampling switch; wherein the capacitive means integrates the analog input signal during an integration phase
Implementation Method 2
during a reset phase, the reset switch is closed such that the terminals of the capacitive means are shorted causing the capacitive means to discharge
Implementation Method 3
during a subsequent integration phase, the reset switch is open and the sampling switch remains closed thereby integrating the analog input signal onto the capacitive means
Data Source
AI summary
A sampling circuit for sampling an analog input signal including: a capacitive means, a reset switch, and a sampling switch; the reset switch and the sampling switch being connected to a signal generator circuit configured to provide periodic reset and sampling control signals to the respective switches for controlling their operation. The respective periodic reset and sampling control signals have equal duty factors and signal periods, and a phase delay with respect to one another being less than the signals' duty factor, thereby forming an overlap period during which the reset switch and the sampling switch remain closed.