Analog Sensing of Memory Cells Using Sample and Hold Circuitry

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Solution Overview

Problem

Traditional solid-state memory devices face inefficiencies in programming and reading operations due to their binary nature, which becomes increasingly troublesome as more bits are stored on each multi-level cell, leading to longer operation times and lower storage capacities compared to hard disk drives.

Innovation Solution

The memory devices utilize analog signals representing the complete threshold voltage range of memory cells, allowing for a single read operation to return multiple bits of information, rather than requiring multiple binary operations to determine each bit, and employ a sample and hold circuitry to manage and compare these analog signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple binary operations are used to read each bit in traditional solid-state memory devices, then data can be read accurately, but operation time increases and storage capacity decreases

Engineering Contradiction:
Improveread operation speedVSAvoidoperation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent merges multiple binary read operations into a single analog read operation by treating the memory cell threshold voltage as a continuous analog value that directly represents multiple bits of data, eliminating the need for sequential binary operations to read each bit

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the read operation parameter from discrete binary voltage levels to continuous analog threshold voltage values, allowing the memory system to read the complete threshold voltage range in a single operation and derive multiple bits of information from the analog signal

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If more bits are stored on each multi-level cell, then storage capacity increases, but the complexity of programming and reading operations increases

Engineering Contradiction:
Improvestorage capacityVSAvoidprogramming and reading operation complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent extracts the complexity from the control logic by directly reading the analog threshold voltage value without requiring complex decoding or multiple operational steps, simplifying the control circuitry while maintaining high storage capacity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent makes the read operation universal by using a single analog read mechanism that can retrieve multiple bits of information simultaneously, making the system adaptable to different storage capacities without requiring different read operation sequences

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If traditional binary operations are used in solid-state memory devices, then device structure remains simple, but storage capacity remains limited compared to hard disk drives

Engineering Contradiction:
Improvedevice structureVSAvoidstorage capacity
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent changes the fundamental parameter representation from discrete binary states to continuous analog threshold voltage values, enabling the memory device to store and retrieve multiple bits per cell while maintaining a relatively simple device structure that leverages existing flash memory architecture

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8976582B2Analog sensing of memory cells in a solid-state memory device
Publication Date: 2015.03.10 MICRON TECHNOLOGY INC
  • US8976582B2 patent drawing
  • US8976582B2 patent drawing
  • US8976582B2 patent drawing

AI summary

A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal.