Analog IC Sub-cell Generation via Automated Layout Partitioning
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Solution Overview
Problem
The complexity of integrated circuit design and manufacturing processes, combined with the need for rapid design changes, necessitates more efficient methods for generating and verifying sub-cells in analog integrated circuits to ensure proper function and reliability.
Innovation Solution
Automated techniques for partitioning analog cells into sub-cells, which involve receiving device specifications, determining cut locations, and performing design rule checking, layout vs. schematic verification, and layout vs. layout verification to generate and verify sub-cells, thereby reducing production time and improving design efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automated design tools are used extensively in the design process, then productivity and design speed are improved, but device complexity increases due to the need to manage and verify numerous sub-cells
Solution Approach 1:
The patent automatically partitions an analog cell layout into multiple sub-cells by identifying cut locations along first and second directions. This segmentation transforms a complex monolithic cell into manageable sub-cells that can be independently verified and stored in a library, reducing the complexity of managing the overall design while maintaining high productivity through automation.
2Manufacturing precision
If manual operations are performed repeatedly due to design changes, then manufacturing precision can be maintained, but loss of time increases
Solution Approach 1:
The system performs preliminary automated verification of sub-cells against design rules during the partitioning process. By pre-identifying cut locations and generating sub-cells with embedded verification data, the system eliminates the need for repeated manual verification operations when design changes occur, maintaining precision while significantly reducing time loss.
Solution Approach 2:
Verified sub-cells are stored in a library as reusable templates. When design changes occur, the system can copy and modify existing verified sub-cells rather than manually recreating and re-verify them from scratch, maintaining design rule compliance while dramatically reducing the time required for iterative design changes.
3Ease of manufacture
If the layout is partitioned into multiple sub-cells, then ease of manufacture is improved through modular design, but device complexity increases due to additional verification requirements
Solution Approach 1:
The layout is automatically partitioned into modular sub-cells with clearly defined boundaries and cut locations. This segmentation enables independent manufacturing and verification of each sub-cell, simplifying the overall manufacturing process while the automated verification system manages the complexity of ensuring all sub-cells meet design rules.
Solution Approach 2:
The automated verification system performs design rule checking, layout vs. schematic verification, and layout vs. layout verification on each sub-cell independently. This self-service approach to verification manages the complexity automatically without requiring manual intervention, enabling modular design to proceed efficiently.
Data Source
AI summary
Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.