Analog Sub-Matrix Computing With Memristor Arrays for Large Matrices
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Solution Overview
Problem
Existing computing technologies face challenges in performing efficient analog computations due to limitations in processing large input matrices, as they often require significant resources and energy for digital conversions and operations.
Innovation Solution
A scalable and configurable circuit using memristor arrays to process input matrices as sub-matrices through parallel pipelined architecture, where memristor arrays perform analog multiplication between vectors, and analog to digital converters generate digital values for combined results, with shared resources to conserve power and resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If large input matrices are processed using traditional digital computation methods, then computational accuracy is maintained, but energy consumption increases significantly and processing speed decreases
Solution Approach 1:
The patent segments large input matrices into smaller sub-matrices that can be processed in parallel by multiple computing units. This segmentation enables the system to leverage analog computing's energy efficiency while maintaining the ability to handle large-scale computations through divided-and-conquer methodology, thus reducing overall energy consumption without sacrificing processing throughput.
Solution Approach 2:
The patent replaces traditional digital mechanical computation systems with analog computing systems that use continuous physical quantities (voltages, currents) to perform computations. This substitution exploits the inherent parallelism of analog circuits, enabling simultaneous processing of multiple operations and significantly improving processing speed while reducing energy consumption compared to sequential digital methods.
2Productivity
If large input matrices are processed using traditional digital computation methods, then complete computational operations can be performed, but processing speed decreases
Solution Approach 1:
The patent divides large matrix processing into smaller sub-matrix operations that can be executed in parallel. This segmentation simplifies the computational architecture by breaking down complex large-scale operations into manageable smaller units, each with simpler internal structure, while achieving high processing speed through parallel execution of these simplified units.
Solution Approach 2:
The patent transitions from sequential one-dimensional processing to parallel multi-dimensional processing by activating multiple computing units simultaneously. This dimensional change in processing architecture enables multiple sub-matrices to be processed concurrently, dramatically improving processing speed without requiring each individual processing unit to be overly complex.
3Use of energy by moving object
If analog computing is used to process large matrices directly, then energy efficiency is improved, but the system cannot accommodate matrices larger than the array size
Solution Approach 1:
The patent segments large input matrices into smaller sub-matrices that fit within the physical constraints of the analog computing array. This segmentation allows the energy-efficient analog computing to be applied to each sub-matrix while the collection of sub-matrix results through parallel processing enables the system to handle arbitrarily large input matrices, thus maintaining energy efficiency without limiting matrix size adaptability.
Solution Approach 2:
The patent creates a universal computing architecture where the same analog computing array can process sub-matrices of various sizes through configurable parallel processing. This multi-functional design allows the system to adapt to different matrix dimensions and computational requirements while maintaining consistent energy efficiency, making the system versatile for various application scenarios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster and more energy-efficient analog computing by breaking down large matrices into smaller sub-matrices for parallel processing, reducing resource consumption and enhancing computational speed while maintaining accuracy.
Implementation Method 1
the fundamental relationship between row voltage and column current in a resistive mesh to realize an analog multiply-accumulate unit
Implementation Method 2
the effect of row activation signal on bit line voltage/current can also be interpreted as a bitwise AND operation between row signal and cell value
Data Source
AI summary
A circuit includes an engine to compute analog multiplication results between vectors of a sub-matrix. An analog to digital converter (ADC) generates a digital value for the analog multiplication results computed by the engine. A shifter shifts the digital value of analog multiplication results a predetermined number of bits to generate a shifted result. An adder adds the shifted result to the digital value of a second multiplication result to generate a combined multiplication result.