Analog Switch Gate Driver With Clamp Bias for Ron Flatness
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Solution Overview
Problem
Existing analog switches introduce errors into signal chains due to variations in on-resistance (Ron) caused by changes in gate-to-source voltage (Vgs), which affects signal processing accuracy.
Innovation Solution
The design incorporates a clamp circuit that maintains a stable gate-to-source voltage across field effect transistors, using a switched current source and a clamp circuit to bias the transistors with a low Vgs, reducing die area and minimizing Ron variations, and includes a p-channel source follower to track input voltage and maintain a constant clamp voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a charge pump is used to bias the switches, then the on-resistance flatness is improved, but the device complexity and die area increase
Solution Approach 1:
The patent extracts and eliminates the charge pump component from the circuit architecture. Instead of using a charge pump to generate high voltage for gate biasing, the invention uses a simplified voltage divider network with resistors R1 and R2 that directly provides the necessary gate-to-source voltage from the available supply rails, thereby reducing device complexity and die area while maintaining on-resistance flatness
Solution Approach 2:
The patent changes the biasing voltage parameters by using a voltage divider configuration that provides a stable gate-to-source voltage (Vgs) of approximately 2.5V. This parameter optimization allows the switches to operate in the saturation region with flat on-resistance characteristics without requiring the high voltages that would necessitate a charge pump
2Manufacturing precision
If a charge pump is used to bias the switches, then the on-resistance flatness is improved, but the die area increases
Solution Approach 1:
The patent removes the charge pump component and its associated circuitry from the die, replacing it with a compact voltage divider network using simple resistors. This extraction eliminates the need for complex voltage multiplication circuits while maintaining the necessary gate bias voltage, thereby significantly reducing the die area occupied by the biasing circuitry
Solution Approach 2:
The patent uses simple, low-cost resistor elements instead of complex active components like charge pumps. These passive resistive elements occupy minimal die area and can be easily fabricated using standard semiconductor processing techniques, providing an area-efficient solution for achieving flat on-resistance
3Reliability
If high gate-to-source voltage is applied to the switches, then the on-resistance decreases, but the on-resistance varies with voltage changes
Solution Approach 1:
The patent creates an equipotential biasing scheme where the gate-to-source voltage is held constant at approximately 2.5V through a voltage divider network. This stable biasing ensures that the switches operate at a fixed operating point in the saturation region, eliminating on-resistance variations that would occur with changing input voltages and achieving both low and stable on-resistance
Solution Approach 2:
The patent optimizes the gate-to-source voltage parameter to approximately 2.5V, which is the optimal value for achieving flat on-resistance characteristics in the saturation region. By carefully selecting this voltage parameter and maintaining it stable through the voltage divider configuration, the invention achieves both low on-resistance and minimal variation with voltage changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances Ron flatness, reducing errors in signal processing by maintaining a stable bias voltage across a wide range of input voltages, thereby improving signal chain accuracy and reducing the need for a charge pump, which simplifies semiconductor integrated circuit fabrication.
Implementation Method 1
The clamp circuit clamps the voltage across the common gate and the common source to prevent damage to the first and second FETs and to bias the FETs
Implementation Method 2
The switched current source supplies a gate current to the common gate
Implementation Method 3
a p-channel source follower to track input voltage and maintain a constant clamp voltage
Implementation Method 4
Due to a change in a gate-to-source voltage (Vgs) applied to bias the analog switches, the on-resistance Ron of the switches vary
Data Source
AI summary
An analog switch includes a first field effect transistor (FET) which has a first terminal coupled to an input voltage terminal, a second terminal coupled to a common source, and a control terminal coupled to a common gate. The switch includes a second FET which has a first terminal coupled to an output voltage terminal, a second terminal coupled to the common source, and a control terminal coupled to the common gate. The switch includes a switched current source which has an input coupled to a high voltage supply terminal and an output coupled to the common gate. The switch includes a clamp circuit which has a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal coupled to the low voltage supply terminal.