Analog Switch Sensitization for Transistor-Level Simulation
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Solution Overview
Problem
Static timing analysis (STA) tools lack accuracy in delay calculations for large integrated circuits due to not enumerating all possible paths, and conventional cell sensitization techniques require human intervention, extensive storage, and are impractical for simultaneous sensitization of multiple cells.
Innovation Solution
The system generates a transistor-level description of a circuit subcircuit by inserting analog switches to apply a sensitization sequence during simulation, allowing independent sensitization of cells without storing internal states, thus avoiding the limitations of conventional methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If STA tool is used for timing analysis, then analysis speed is improved, but measurement precision deteriorates
Solution Approach 1:
The patent divides the circuit into subcircuits that require transistor-level simulation and the rest of the circuit that can use STA. This segmentation allows the high-speed STA tool to analyze most of the circuit while only the critical subcircuits undergo time-consuming transistor-level simulation, thus maintaining overall analysis speed while improving precision for critical paths.
Solution Approach 2:
The patent introduces an intermediary process that identifies which subcircuits require transistor-level simulation and prepares them for simulation. This intermediary step acts as a bridge between the fast STA tool and the accurate but slow transistor-level simulator, allowing the system to leverage both approaches effectively.
2Reliability
If conventional cell sensitization technique is used, then cell sensitization can be achieved, but device complexity increases
Solution Approach 1:
The patent extracts the sensitization requirement from the overall simulation process and handles it separately through automatic identification of cells needing sensitization and generation of appropriate test patterns. This separates the sensitization function from the main simulation flow, reducing complexity in the overall system.
Solution Approach 2:
The patent implements automatic cell sensitization where the tool itself identifies which cells need sensitization and generates the necessary test patterns without requiring external intervention. This self-service approach eliminates the need for manual sensitization setup and reduces the complexity of implementing sensitization in the workflow.
3Reliability
If conventional cell sensitization technique is used, then cell sensitization can be achieved, but loss of time increases
Solution Approach 1:
The patent performs cell sensitization preparation in advance by automatically identifying cells that need sensitization and generating appropriate test patterns before the main simulation begins. This preliminary action ensures that cells are properly sensitized when needed during simulation, avoiding time losses during the actual simulation process.
Solution Approach 2:
The patent changes the simulation parameters and approach by using automatic sensitization identification and pattern generation, which optimizes the simulation setup to minimize the time required for sensitization while ensuring proper cell states for accurate delay measurement.
4Measurement precision
If transistor-level simulation is used for entire circuit, then measurement precision is improved, but productivity deteriorates
Solution Approach 1:
The patent segments the circuit to identify only the critical subcircuits that require transistor-level simulation for accurate delay measurement. By applying transistor-level simulation only to these identified subcircuits rather than the entire circuit, the system maintains high measurement precision for critical paths while preserving overall analysis productivity.
Data Source
AI summary
One embodiment of the present invention provides systems and techniques for generating a transistor-level description of a subcircuit. A user may want to simulate a subcircuit in a circuit using a transistor-level simulator, and one or more cells in the subcircuit may need to be sensitized so that the cells are in a desired state when the subcircuit is simulated. An embodiment modifies the subcircuit by inserting analog switches in front of the cells that need to be sensitized, so that the analog switches can be used to apply a sensitization sequence to the cells during the transistor-level simulation. The embodiment can then generate a transistor-level description of the modified subcircuit. Next, the transistor-level description of the subcircuit can be stored, thereby enabling the transistor-level simulator to simulate the subcircuit.