Analog Test Bus Isolation for Multi-Power-Domain ICs

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Solution Overview

Problem

Integrated circuits with multiple power domains face challenges in testing due to latch-up and isolation issues when different sets of analog circuitry are coupled to a common analog test bus, leading to accuracy problems and potential damage.

Innovation Solution

Employing multiple transmission gates and protection devices between analog circuitry and the analog test bus, controlled by specific control signals, to isolate and protect analog circuitry during testing, reducing latch-up and current leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple sets of analog circuitry from different power domains are coupled to the same analog test bus, then the testing capability is improved, but latch-up and isolation problems occur

Engineering Contradiction:

Improvetesting capabilityVSAvoidlatch-up and isolation problems

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

Transmission gates are introduced as intermediary components between the analog test bus and analog circuitry from different power domains. These transmission gates act as controlled switches that isolate incompatible power domains while allowing selective connection during testing, preventing latch-up conditions while maintaining testing capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The analog test bus system is segmented into multiple isolated segments, each serving specific power domains. By dividing the test bus into separate segments that can be independently controlled, the system allows testing of different power domains without causing interference or latch-up between them.

Inventive Principle:

Principle #1Segmentation

2Reliability

If multiple analog test buses are used to address latch-up and isolation problems, then reliability is improved, but integrated circuit area increases

Engineering Contradiction:

Improvelatch-up and isolation problemsVSAvoidintegrated circuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Multiple test bus functions are merged into a single shared analog test bus through the use of transmission gates. Instead of providing separate dedicated test buses for each power domain, the system combines them into one bus that can be selectively connected to different circuitry through controlled switches, reducing overall area while maintaining reliability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The test bus configuration is made dynamic through the use of controllable transmission gates that can selectively connect or disconnect different analog circuitry from the same power domain to the test bus. This dynamic switching capability allows a single test bus to serve multiple functions that would otherwise require multiple static test buses.

Inventive Principle:

Principle #15Dynamics

3Difficulty of detecting and measuring

If on-chip monitors are employed to address isolation problems, then measurement capability is improved, but accuracy and measurement range are limited

Engineering Contradiction:

Improvemeasurement capabilityVSAvoidaccuracy and measurement range

Core Design Contradiction:

Difficulty of detecting and measuringVSMeasurement precision

Solution Approach 1:

Transmission gates serve as intermediary components that provide clean, controlled isolation between the test bus and analog circuitry, replacing on-chip monitors. This intermediary approach maintains signal integrity and measurement accuracy by preventing direct exposure to parasitic voltages while still enabling comprehensive measurement capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12474399B2Analog test devices for integrated circuits with multiple power domains

Publication Date: 2025.11.18 NXP BV

AI summary

An analog circuit includes an analog test bus; a plurality of analog circuits including a first analog circuit, each of the plurality of analog circuits associated with a corresponding one of a plurality of power domains; a first plurality of transmission gates coupled between the first analog circuit and the analog test bus; and a first protection device coupled between the first plurality of transmission gates and a ground reference.