Analog Circuit Test Point Selection via Defect-Driven Block Outputs

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Solution Overview

Problem

Existing test suites for analog and mixed signal circuits are incomplete, often failing to detect defects due to the difficulty in selecting appropriate test points, particularly in transistor-level netlists where nodes are difficult to access and signal representation differs from digital circuits.

Innovation Solution

A system that partitions circuit designs into channel-connected blocks, simulates with and without defects, determines output node differences exceeding a threshold, and generates tests to measure signals at these nodes, thereby expanding test coverage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing test suites are used for analog and mixed signal circuits, then the testing process is simple, but test coverage is incomplete and defects are not detected

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidtest generation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The circuit design is partitioned into channel-connected blocks by disconnecting at power-nets, creating manageable segments that can be analyzed independently. This segmentation enables systematic identification of output nodes while maintaining completeness in defect detection coverage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary simulation by injecting potential defects into the circuit design before actual testing. This preliminary action identifies which output nodes will exhibit detectable signal differences, allowing the test generator to focus only on those nodes and expand coverage efficiently.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If test points are selected in transistor-level netlists, then comprehensive testing is possible, but nodes are difficult to access and selection is complex

Engineering Contradiction:
Improvetest coverageVSAvoidtest point selection ease
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The system extracts only the necessary output nodes from the full circuit design by analyzing simulated defect responses. Instead of dealing with all nodes in the transistor-level netlist, the system identifies and extracts specifically those nodes where defect-induced signal differences exceed the threshold, simplifying test point selection while maintaining comprehensive coverage.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If all output nodes are tested to ensure complete coverage, then defect detection is maximized, but testing time increases

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidtest generation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system changes the parameter threshold for node selection by comparing simulated output signals against a defined threshold value. This parameter-based filtering automatically identifies the minimal set of output nodes that will detect all potential defects, eliminating the need to test all nodes while ensuring complete defect detection coverage.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12481813B2Test point insertion in analog circuit design testing
Publication Date: 2025.11.25 SYNOPSYS INC
  • US12481813B2 patent drawing
  • US12481813B2 patent drawing
  • US12481813B2 patent drawing

AI summary

A system and method for inserting test points during circuit design testing are presented. The method includes partitioning a circuit design into a plurality of blocks and determining a first potential defect and a second potential defect for the circuit design. The method also includes simulating the circuit design by injecting, into the circuit design, the first potential defect to produce a first set of outputs of the plurality of blocks and simulating the circuit design by injecting, into the circuit design, the second potential defect to produce a second set of outputs of the plurality of blocks. The method further includes determining a set of output nodes of the plurality of blocks and generating a test that, when executed, measures signals at the set of output nodes.