Programmable Analog Tile Bus for PMIC Configuration
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Solution Overview
Problem
Existing power management integrated circuits (PMICs) require significant engineering effort and time to customize for specific customer requirements due to their irregular shapes and shared circuitry, leading to increased costs and longer time-to-market, as well as substantial unused circuitry in the final product.
Innovation Solution
A Multi-Tile Power Management Integrated Circuit (MTPMIC) composed of regularly shaped, programmable PMIC tiles with a standardized bus for signal communication and writable configuration registers, allowing for easy selection, placement, configuration, and programming using the Analog Tile Selection, Placement, Configuration, and Programming (ATSPCP) tool, which simplifies the design process and eliminates the need for custom routing layers and memory structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional PMIC design with irregular shapes and shared circuitry is used, then functional capability can be achieved, but engineering effort and time to market increase significantly
Solution Approach 1:
The patent divides the PMIC into separate functional tiles (voltage regulator tile, LDO tile, battery charger tile, etc.) that can be independently selected and configured. Each tile is a self-contained module with standardized interfaces, allowing custom combinations based on customer requirements without redesigning the entire circuit layout.
Solution Approach 2:
The patent creates a universal tile architecture where standardized bus portions and link portions enable different tile types to interconnect and function together. The same standardized interface structure allows various functional tiles to work in combination, providing multi-functionality without requiring custom routing for each configuration.
2Adaptability or versatility
If traditional PMIC design with irregular shapes is used, then functional capability can be achieved, but device complexity increases
Solution Approach 1:
The patent segments the PMIC into regular-shaped tiles with standardized bus portions. This segmentation transforms the complex irregular layout into a modular structure where each tile has a consistent interface pattern, simplifying the overall design process and reducing layout complexity while maintaining functional versatility.
Solution Approach 2:
The patent changes the geometric parameter of tile shapes from irregular to regular (rectangular with standardized dimensions). This parameter change enables systematic arrangement of tiles using grid-based placement, dramatically simplifying layout generation and reducing design complexity compared to custom irregular shapes.
3Adaptability or versatility
If PMIC is designed with substantial circuitry to meet various requirements, then adaptability is improved, but cost and size increase
Solution Approach 1:
The patent segments functionality into separate optional tiles rather than including all possible functions in a single large PMIC. Customers can select only the tiles they need (e.g., voltage regulator tile, LDO tile, battery charger tile), reducing the total quantity of circuitry while maintaining adaptability to different requirements.
Solution Approach 2:
The patent applies partial action by including only the necessary functional tiles in each PMIC configuration rather than designing for all possible requirements. This allows customization where customers get exactly the functionality they need without the excessive circuitry of a fully-featured design.
Data Source
AI summary
A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.