Analog Circuit Transistor Sizing via SMT Obfuscation
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Solution Overview
Problem
Existing analog circuit design methods face challenges in efficiently determining transistor sizes that meet performance constraints while implementing parameter obfuscation, leading to design overhead and security vulnerabilities due to multiple correct keys and limited deviation in performance when incorrect keys are applied.
Innovation Solution
The use of satisfiability modulo theory (SMT) based design space exploration, specifically through analog satisfiability (aSAT) algorithms, to automatically determine transistor widths and lengths that satisfy circuit constraints, limiting the number of effective keys and ensuring secure operation by masking critical parameters like gain and gain-bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional manual methods are used to determine transistor sizes for parameter obfuscation, then design flexibility is maintained, but design time increases and security is compromised due to multiple correct keys
Solution Approach 1:
The patent replaces manual trial-and-error design methods with an automated SMT-based computational system. The SMT solver automatically determines transistor sizes that satisfy both performance constraints and security requirements, eliminating the need for iterative manual adjustment and significantly reducing design time while ensuring unique correct keys for obfuscation.
Solution Approach 2:
The design system performs self-verification by automatically checking whether the determined transistor sizes satisfy both circuit performance constraints and security requirements. The SMT solver inherently verifies the correctness of the solution by proving that the derived transistor dimensions uniquely determine the correct key, eliminating the need for external verification steps.
2Reliability
If transistor sizes are obfuscated to limit correct keys, then security improves, but device complexity increases
Solution Approach 1:
The patent changes the parameters of existing transistors (width and length dimensions) to create obfuscation without adding new circuit components. By adjusting the physical dimensions of transistors within acceptable design ranges, the system achieves security through parameter variation rather than structural complexity, maintaining circuit simplicity while limiting correct keys to a single unique solution.
3Loss of time
If SMT-based automated sizing is used, then design time reduces and security improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different precision requirements to different transistor dimensions based on their sensitivity to performance and security parameters. The SMT solver identifies which transistor width and length parameters critically affect the obfuscation security and performance, allowing relaxed tolerances for less sensitive dimensions while maintaining strict precision only where necessary, thereby reducing overall manufacturing precision requirements.
Data Source
AI summary
An approach is described for enhancing the security of analog circuits using Satisfiability Modulo Theory (SMT) based design space exploration. The technique takes as inputs generic circuit equations and performance constraints and, by exhaustively exploring the design space, outputs transistor sizes that satisfy the given constraints. The analog satisfiability (aSAT) methodology is applied to parameter biasing obfuscation, where the width of a transistor is obfuscated to mask circuit properties, while also limiting the number of keys that produce the target performance requirements.