Analog Verification Command Translation System
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Solution Overview
Problem
The verification of analog and mixed signal integrated circuits is hindered by increasing complexity, leading to computational demands and resource inefficiencies, with current methods being manual, time-consuming, and lacking in traceability to product specifications.
Innovation Solution
A computer-implemented method translates verification commands using indirect branch contribution statements, linking critical parameters to a specification database, and generating netlists for efficient simulation and verification processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If manual verification methods are used for analog and mixed signal circuits, then verification can be performed with simple tools, but the process becomes time-consuming and labor-intensive
Solution Approach 1:
The patent introduces an intermediary translation system that converts high-level verification commands into simulator-specific instructions. This intermediary layer automates the verification process while maintaining ease of use, eliminating the need for manual interpretation and significantly reducing verification time without sacrificing simplicity.
Solution Approach 2:
The verification system performs self-service through automated command translation and execution. The system automatically translates verification commands, manages simulation processes, and generates results without requiring manual intervention, thereby reducing both time consumption and labor intensity while maintaining process simplicity.
2Reliability
If extensive verification review is conducted to ensure circuit functionality, then verification accuracy improves, but computational processing power requirements increase dramatically
Solution Approach 1:
The patent segments the verification process into distinct phases: command translation, simulation execution, and result analysis. By dividing the extensive verification review into manageable segments, the system maintains high verification accuracy while reducing peak computational processing power requirements through efficient resource utilization across multiple processing stages.
3Productivity
If verification commands are translated automatically, then productivity increases and manual interpretation is reduced, but the device complexity increases due to translation infrastructure
Solution Approach 1:
The translation system is designed with universal functionality to handle multiple verification command types and simulator interfaces through a single unified platform. This multi-functionality approach increases verification productivity while managing device complexity by consolidating translation capabilities into a versatile system rather than requiring separate complex translators for each command type.
4Reliability
If traceability to product specifications is implemented, then verification compliance improves, but the complexity of linking parameters to specifications increases
Solution Approach 1:
The patent implements feedback mechanisms that automatically track and report verification results against product specifications. The system provides continuous feedback on compliance status, maintaining high verification compliance while managing parameter linking complexity through automated tracking and reporting systems that reduce manual intervention requirements.
Data Source
AI summary
A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.